Abstract: In a static induction semiconductor device, particular a high power static induction semiconductor device, recessed portions 12 are formed in one surface of a silicon substrate 11 of one conductivity type, gate regions 13 of the other conductivity type are formed at bottoms of the recessed portions, recessed portions 14 are formed at portions surrounded by adjacent gate regions, cathode short-circuit regions 15 of the other conductivity type are formed as an island at bottoms of the recessed portions to be extended to the surface of the silicon substrate. Cathode regions 17 extending up to the surface of the silicon substrate in succession to channel regions 16 surrounded by the cathode regions 13 and cathode short-circuit regions 15, are formed. A cathode electrode substrate 21 is formed to be contacted with the cathode short-circuit regions 15 and cathode regions 17.

Abstract: A normally-off semiconductor device with gate regions formed in a high-quality base is manufactured by forming a P.sup.+ layer in a lower surface of an N.sup.- substrate, selectively forming P.sup.+ gate regions in an upper surface of the N.sup.- substrate, forming intergate P.sup.+ regions in the upper surface of the N.sup.- substrate between the P.sup.+ gate regions, forming an N.sup.+ layer in an upper surface of an N.sup.- substrate, joining the N.sup.- substrate and the N.sup.- substrate to each other by heating them at about 800.degree. C. in a hydrogen atmosphere while the upper surface of the N.sup.- substrate and a lower surface of the N.sup.- substrate are being held against each other, and forming an anode electrode and a cathode electrode.

Abstract: A semiconductor device that includes a recessed portion formed by isotropic-etching through an opening in an oxide layer on a surface of the semiconductor substrate, an opening formed in an oxide layer formed on the inner surface of the recessed portion by anisotropic etching, a recessed portion formed adjacent another recessed portion by isotropic etching through the opening. An overhang portion in the oxide layers at the opening is used as a mask in successive etching steps, and the isotropic and anistropic etching steps are repeated through the same mask, to eliminate errors in stacking masks and obtaining a deep notched gate structure within a short period. A cross-sectional shape of the recessed portion includes a plurality of curved recessed portions of different curvatures. A semiconductor device thus formed includes a recessed portion having a high aspect (length/width) ratio, and a depth larger than the width.

Abstract: A vertical type semiconductor device having a semiconductor substrate and at least one gate electrode structure formed in the semiconductor substrate for controlling a current flow across the semiconductor substrate. The semiconductor substrate is formed by a silicon substrate, a silicon carbide or diamond layer epitaxially deposited on the silicon substrate, and a silicon layer epitaxially deposited on the silicon carbide or diamond layer. Recesses are formed in the silicon layer and gate electrodes are provided in the recesses via silicon oxide films. Source or emitter regions are formed in portions of the silicon layer which are brought into contact with the silicon oxide films by inverting the conductivity of these portions. Source or emitter electrodes are provided on the source or emitter regions, and a drain or collector electrode is provided on a rear surface of the silicon substrate.

Abstract: A vertical type semiconductor device having a semiconductor substrate and at least one gate electrode structure formed in the semiconductor substrate for controlling a current flow across the semiconductor substrate. The semiconductor substrate is formed by a silicon substrate, a silicon carbide or diamond layer epitaxially deposited on the silicon substrate, and a silicon layer epitaxially deposited on the silicon carbide or diamond layer. Recesses are formed in the silicon layer and gate electrodes are provided in the recesses via silicon oxide films. Source or emitter regions are formed in portions of the silicon layer which are brought into contact with the silicon oxide films by inverting the conductivity of these portions. Source or emitter electrodes are provided on the source or emitter regions, and a drain or collector electrode is provided on a rear surface of the silicon substrate.

Abstract: A method of manufacturing a joined-type semiconductor device having a gate structure. The semiconductor device includes a first and second semiconductor substrates each having a substrate body, and a first and a second main surfaces which are opposite to each other. A gate structure is formed in the first main surface of the first substrate. A highly-doped semiconductor layer is formed in the first main surface of the second substrate and has an impurity-concentration which is higher than that of the substrate body of the second substrate. The first main surfaces of the two substrates are joined with each other, by subjecting the two substrates to a heat treatment so that impurities in the highly-doped semiconductor layer of the second substrate are driven into the surface region of the first substrate, and a diffusion layer is thereby formed in the first main surface of the first substrate.

Abstract: In a surface of a silicon substrate of one conductivity type, there are formed a plurality of depressions or recesses, gate regions of opposite conductivity type are formed at bottoms of respective recesses, gate electrodes are provided on respective gate regions, and an electrically conductive block is joined to the surface of the semiconductor substrate. Between the surface of the semiconductor substrate and the electrically conductive block a contact region having a high impurity concentration and/or an electrically conductive material layer may be provided in order to improve electrical and mechanical properties of the contact between the semiconductor substrate and the electrically conductive block. The gate region can have a high impurity concentration and a distance between a channel region and the electrically conductive block can be very small.

Abstract: A gate structure including semiconductor regions each having a high impurity-concentration and being formed within respective one of recessed portions provided in a surface of a first semiconductor substrate, and then a second semiconductor substrate is brought into contact with the surface of the first semiconductor substrate. The gate structure may be formed such that each of the recessed portions is completely or partially filled with the gate structure. When the gate structure includes electrically good-conductive films of a high melting point metal or the like each formed in respective one of the recessed portions, the gate resistance can be further decreased.

Abstract: A P.sup.+ layer is formed on the lower surface of an N.sup.- substrate, and recesses are defined in the upper surface of the N.sup.- substrate. Then, P.sup.+ gate regions and bottom gate regions are formed in side walls and bottoms of the recesses. The N.sup.- substrate and an N.sup.- substrate are ultrasonically cleaned to remove impurities therefrom, then cleaned by pure water, and dried by a spinner. Then, while lands on the upper surface of the N.sup.- substrate are being held against the surface of the N.sup.- substrate, the N.sup.- substrates are joined to each other by heating them at 800.degree. C. in a hydrogen atmosphere.

Abstract: A gate structure including semiconductor regions each having a high impurity-concentration and being formed within respective one of recessed portions provided in a surface of a first semiconductor substrate, and then a second semiconductor substrate is brought into contact with the surface of the first semiconductor substrate. The gate structure may be formed such that each of the recessed portions is completely or partially filled with the gate structure. When the gate structure includes electrically good-conductive films of a high melting point metal or the like each formed in respective one of the recessed portions, the gate resistance can be further decreased.

Abstract: A normally-off semiconductor device with gate regions formed in a high-quality base is manufactured by forming a P.sup.+ layer in a lower surface of an N.sup.- substrate, selectively forming P.sup.+ gate regions in an upper surface of the N.sup.- substrate, forming intergate P.sup.+ regions in the upper surface of the N.sup.- substrate between the P.sup.+ gate regions, forming an N.sup.+ layer in an upper surface of an N.sup.- substrate, joining the N.sup.- substrate and the N.sup.- substrate to each other by heating them at about 800.degree. C. in a hydrogen atmosphere while the upper surface of the N.sup.- substrate and a lower surface of the N.sup.- substrate are being held against each other, and forming an anode electrode and a cathode electrode.

Abstract: A method of manufacturing a joined-type semiconductor device having a gate structure. The semiconductor device includes a first and second semiconductor substrates each having a substrate body, and a first and a second main surfaces which are opposite to each other. A gate structure is formed in the first main surface of the first substrate. A highly-doped semiconductor layer is formed in the first main surface of the second substrate and has an impurity-concentration which is higher than that of the substrate body of the second substrate. The first main surfaces of the two substrates are joined with each other, by subjecting the two substrates to a heat treatment so that impurities in the highly-doped semiconductor layer of the second substrate are driven into the surface region of the first substrate, and a diffusion layer is thereby formed in the first main surface of the first substrate.

Abstract: In a surface of a silicon substrate of one conductivity type, there are formed a plurality of depressions or recesses, gate regions of opposite conductivity type are formed at bottoms of respective recesses, gate electrodes are provided on respective gate regions, and an electrically conductive block is joined to the surface of the semiconductor substrate. Between the surface of the semiconductor substrate and the electrically conductive block a contact region having a high impurity concentration and/or an electrically conductive material layer may be provided in order to improve electrical and mechanical properties of the contact between the semiconductor substrate and the electrically conductive block. The gate region can have a high impurity concentration and a distance between a channel region and the electrically conductive block can be very small.

Abstract: After selectively forming P.sub.+ -type gate regions 14 in the upper surface of a first N.sup.- -type semiconductor substrate 10, gate electrodes 30 are selectively formed on the P.sup.+ -type gate regions. A P.sup.+ -type layer 12 is formed in the lower surface of the N.sup.- -type substrate 10. Recessed portions 26 which can house the gate electrodes are formed in the lower surface of the second N.sup.- -type semiconductor substrate 20 and an N.sup.+ -type layer 22 is formed in the upper surface thereof. After removing impurities from the surfaces of the first and second semiconductor substrates 10 and 20 by RCA cleaning, the surfaces are cleaned with a pure water and are dried by a spinner. Then the substrates 10 and 20 are joined to each other by heating the substrates 10 and 20 at 700.degree.-1100.degree. C. in an H.sub.

Abstract: A semiconductor device, by which a base in which gates are buried can be formed by the junction of semiconductor substrates to each other at a lower temperature, and a fabrication process thereof are provided. Recesses are defined in the top of an N.sup.- substrate. A P.sup.+ layer is formed on the underside of the N.sup.- substrate. P.sup.+ -Gate regions are each formed in an area ranging from the bottom to lower side portions of the recesses. A metal layer composed of an Au-Sb alloy is formed on the underside of the N.sup.+ substrate. The N.sup.- substrate and the N.sup.+ substrate are subjected to a treatment for removing impurities thereon with an aqueous solution of sulfuric acid and hydrogen peroxide, washed with purified water and dried by a spin dryer. The N.sup.- substrate and the N.sup.+ substrate are heated at about 350.degree. C.

Abstract: A P.sup.+ layer is formed on the lower surface of an N.sup.- substrate, and recesses are defined in the upper surface of the N.sup.- substrate. Then, P.sup.+ gate regions and bottom gate regions are formed in side walls and bottoms of the recesses. The N.sup.- substrate and an N.sup.- substrate are ultrasonically cleaned to remove impurities therefrom, then cleaned by pure water, and dried by a spinner. Then, while lands on the upper surface of the N.sup.- substrate are being held against the surface of the N.sup.- substrate, the N.sup.- substrate are joined to each other by heating then at 800.degree. C. in a hydrogen atmosphere.

Abstract: A semiconductor device, by which a base in which gates are buried can be formed by the junction of semiconductor substrates to each other at a lower temperature, and a fabrication process thereof are provided. Recesses are defined in the top of an N.sup.- substrate. A P.sup.+ layer is formed on the underside of the N.sup.- substrate. P.sup.+ -Gate regions are each formed in an area ranging from the bottom to lower side portions of the recesses. A metal layer composed of an Au-Sb alloy is formed on the underside of the N.sup.+ substrate. The N.sup.- substrate and the N.sup.+ substrate are subjected to a treatment for removing impurities thereon with an aqueous solution of sulfuric acid and hydrogen peroxide, washed with purified water and dried by a spin dryer. The N.sup.- substrate and the N.sup.+ substrate are heated at about 350.degree. C.

Abstract: After selectively forming P.sup.+ -type gate regions 14 in the upper surface of a first N.sup.- -type semiconductor substrate 10, gate electrodes 30 are selectively formed on the P.sup.+ -type gate regions. A P.sup.+ -type layer 12 is formed in the lower surface of the N.sup.- -type substrate 10. Recessed portions 26 which can house the gate electrodes are formed in the lower surface of the second N.sup.- -type semiconductor substrate 20 and an N.sup.+ -type layer 22 is formed in the upper surface thereof. After removing impurities from the surfaces of the first and second semiconductor substrates 10 and 20 by RCA cleaning, the surfaces are cleaned with a pure water and are dried by a spinner. Then the substrates 10 and 20 are joined to each other by heating the substrates 10 and 20 at 700-1100.degree. C. in an H.sub.2 atmosphere, while the upper surface of the first semiconductor substrate 10 is brought into contact with projected portions 29 on the lower surface of the second semiconductor substrate 20.

Abstract: A reverse blocking type semiconductor device capable of being rapidly turned off is disclosed in which a semiconductor substrate includes four semiconductor layers in a region sandwiched between a pair of principal surfaces in such a manner that adjacent ones of these layers are different in conductivity type from each other, one outermost layer of the layers is surrounded by the layer adjacent to the one outermost layer, the one outermost layer and the layer adjacent thereto are exposed to one principal surface, a cathode electrode kept in low-resistance contact with one outermost layer, a gate electrode is kept in low-resistance contact with the layer adjacent to the one outermost layer and lies in close proximity to the one outermost layer, an anode electrode is kept in low-resistance contact with the other outermost layer at the other principal surface, and a main operating region of the other outermost layer has an impurity concentration gradient in a direction parallel to the anode electrode.

Abstract: Disclosed is a field controlled thyristor in which a first semiconductor region of N.sup.+ -type, a second semiconductor region of N-type, third semiconductor regions of P-type, a fourth semiconductor region of N.sup.- -type and a fifth semiconductor region of P.sup.+ -type are formed in a semiconductor substrate having two main surfaces, the first, second and third semiconductor regions being exposed in the first main surface and the fifth semiconductor region being exposed in the second main surface; and the third semiconductor regions of P-type are spaced from each other by a predetermined spacing. The third semiconductor regions are connected with surface-exposed semiconductor regions exposed in the first main surface. The impurity concentration in the second semiconductor region decreases from the first semiconductor region toward the third semiconductor region so that a low forward voltage drop can be achieved along with a high reverse blocking voltage.