Patents by Inventor Yoshiro Ishizawa

Yoshiro Ishizawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5905405
    Abstract: In a quadrature circuit, when a large frequency variation is detected, the carrier reproduction is conducted by using the carrier reproduction loop having a signal distortion but a small delay, and then, if the reproduced carrier becomes stable at some degree, the carrier reproduction is conducted by using the carrier reproduction loop having a less signal distortion but a large delay. When the number of the errors detected by an error detecting and correcting circuit is larger than a predetermined value, a selector supplies a digital in-phase signal and a digital quadrature signal outputted from A/D converters located before a waveform equalizer, to a carrier phase error detecting circuit which generates a digital phase error signal feedback through a D/A converter to a local carrier oscillator.
    Type: Grant
    Filed: August 11, 1997
    Date of Patent: May 18, 1999
    Assignee: NEC Corporation
    Inventor: Yoshiro Ishizawa
  • Patent number: 4926175
    Abstract: An analog-digital converting circuit comprises an analog amplifying circuit having different amplification factors and an input connected to an analog signal input terminal. A first selector is connected at a corresponding number of inputs to receive the plurality of amplified analog signals, respectively. The first selection circuit outputs one analog signal selected from the received amplified analog signals, to an analog-digital converter. A second selector is connected at its an input to receive a digital signal from the analog-digital converter and has a plurality of outputs for outputting the received digital signal from one sequentially alternatively selected from the plurality of outputs. A coefficient multiplying circuit is connected to the outputs of the second selector, and generates multiplied digital signals obtained by multiplying the outputs of the second selector by different coefficeints.
    Type: Grant
    Filed: April 20, 1989
    Date of Patent: May 15, 1990
    Assignee: NEC Corporation
    Inventors: Yoshiro Ishizawa, Hiroshi Morito