Patents by Inventor Yoshisato Yokoyama
Yoshisato Yokoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240021241Abstract: Disclosed herein are related to a memory device. In one aspect, the memory device includes a drive circuit coupled to a first line and a second line. In one aspect, the drive circuit is configured to apply, according to a first control signal having a first state, a data signal to either one of the first line or the second line to write data at a memory cell. In one aspect, the memory device includes a pre-charge circuit configured to set, according to a second control signal having a second state, voltages at the first line and the second line to a predetermined voltage level. In one aspect, the memory device includes an equalizer configured to electrically decouple the first line from the second line, according to the first control signal having the first state and the second control signal having the second state.Type: ApplicationFiled: January 30, 2023Publication date: January 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Masaru Haraguchi, Yoshisato Yokoyama, Yorinobu Fujino
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Patent number: 11264087Abstract: A semiconductor device includes a first wiring having a first portion, a second portion, a third portion provided between the first portion and the second portion, memory cells connected to the third portion of the first wiring, a field effect transistor having a drain connected to the second portion, and a gate, and a second wiring provided in parallel with the first wiring. The third portion of the first wiring includes a fourth portion located nearest to the first portion and a fifth portion located nearest to the second portion. The first wiring further includes a sixth portion disposed between the first portion and the fourth portion. The memory cells include a first memory cell connected to the fourth portion and a second memory cell connected to the fifth portion. The second wiring is electrically connected between the sixth portion and the gate of the field effect transistor.Type: GrantFiled: April 10, 2020Date of Patent: March 1, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshisato Yokoyama, Makoto Yabuuchi
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Patent number: 11081169Abstract: A semiconductor device has a first memory circuit comprising a first memory cell comprising a first field effect transistor, a second memory circuit comprising a second memory cell comprising a second field effect transistor, and a regulator for converting the first power supply potential to a second voltage value lower than the voltage value of the first power supply potential. The second gate length of the second field effect transistor is longer than the first gate length of the first field effect transistor, the first memory cell is supplied with a second power supply potential through regulator, and the second memory cell is supplied with a first power supply potential.Type: GrantFiled: September 20, 2019Date of Patent: August 3, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Daisuke Nakamura, Yoshisato Yokoyama
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Patent number: 10964404Abstract: A semiconductor device capable of detecting whether test operation is normal is provided. The semiconductor device includes a plurality of memory cells arranged in a matrix, a plurality of word lines provided corresponding to each of the rows of the plurality of memory cells respectively, a decoder for generating driving signals for driving the plurality of word lines, and a detection circuit provided between the plurality of word lines and the decoder for simultaneously raising the plurality of word lines by test operation and detecting whether or not the rising state of the plurality of word lines is normal.Type: GrantFiled: August 14, 2019Date of Patent: March 30, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshisato Yokoyama, Shinji Tanaka
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Patent number: 10897248Abstract: A MOS transistor is allowed to recover from BTI degradation even when an operation mode signal is inactive. A semiconductor device includes a drive circuit coupled to a controlled circuit via a delay element. The drive circuit includes first and second MOS transistors coupled in series to each other. The first MOS transistor is controlled to be in an OFF state when the operation mode signal is active. When the operation mode signal is inactive, the first MOS transistor is controlled to be in the OFF state at least temporarily while the second MOS transistor is controlled to be in the OFF.Type: GrantFiled: February 26, 2019Date of Patent: January 19, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshisato Yokoyama, Toshiaki Sano
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Patent number: 10830814Abstract: A semiconductor device includes a memory cell array, a plurality of word lines, a plurality of bit line pairs, a column selection circuit coupling a bit line pair in a selected column in the plurality of bit line pairs to first and second output signal lines on the basis of a column selection signal, and a sense amplifier amplifying the voltage difference between the first and second output signal lines. The semiconductor device further includes: a scan flip flop to which the data can be input via a scan chain; and a voltage setting circuit setting the first and second output signal lines to voltage according to the data held in the scan flip flop in a scan test.Type: GrantFiled: February 26, 2019Date of Patent: November 10, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Yoshisato Yokoyama
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Publication number: 20200342936Abstract: A semiconductor device includes a first wiring having a first portion, a second portion, a third portion provided between the first portion and the second portion, memory cells connected to the third portion of the first wiring, a field effect transistor having a drain connected to the second portion, and a gate, and a second wiring provided in parallel with the first wiring. The third portion of the first wiring includes a fourth portion located nearest to the first portion and a fifth portion located nearest to the second portion. The first wiring further includes a sixth portion disposed between the first portion and the fourth portion. The memory cells include a first memory cell connected to the fourth portion and a second memory cell connected to the fifth portion. The second wiring is electrically connected between the sixth portion and the gate of the field effect transistor.Type: ApplicationFiled: April 10, 2020Publication date: October 29, 2020Inventors: Yoshisato YOKOYAMA, Makoto YABUUCHI
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Patent number: 10811405Abstract: A semiconductor device includes a semiconductor substrate, a memory cell formed on the semiconductor substrate, a word line connected to the memory cell, and an auxiliary line connected to the word line.Type: GrantFiled: July 31, 2019Date of Patent: October 20, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yuta Yoshida, Makoto Yabuuchi, Yoshisato Yokoyama
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Publication number: 20200143876Abstract: A semiconductor device has a first memory circuit comprising a first memory cell comprising a first field effect transistor, a second memory circuit comprising a second memory cell comprising a second field effect transistor, and a regulator for converting the first power supply potential to a second voltage value lower than the voltage value of the first power supply potential. The second gate length of the second field effect transistor is longer than the first gate length of the first field effect transistor, the first memory cell is supplied with a second power supply potential through regulator, and the second memory cell is supplied with a first power supply potential.Type: ApplicationFiled: September 20, 2019Publication date: May 7, 2020Inventors: Daisuke NAKAMURA, Yoshisato YOKOYAMA
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Publication number: 20200075115Abstract: A semiconductor device capable of detecting whether test operation is normal is provided. The semiconductor device includes a plurality of memory cells arranged in a matrix, a plurality of word lines provided corresponding to each of the rows of the plurality of memory cells respectively, a decoder for generating driving signals for driving the plurality of word lines, and a detection circuit provided between the plurality of word lines and the decoder for simultaneously raising the plurality of word lines by test operation and detecting whether or not the rising state of the plurality of word lines is normal.Type: ApplicationFiled: August 14, 2019Publication date: March 5, 2020Inventors: Yoshisato YOKOYAMA, Shinji TANAKA
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Patent number: 10552261Abstract: A selection decoder controls levels of a plurality of selection signals based on an address bit having at least one or more bits. A memory module is selected when its corresponding selection signal is at an activated level, and data can be read and written therein. A failure determination unit determines whether or not the selection decoder is in a failed state based on the levels of the plurality of selection signals.Type: GrantFiled: May 21, 2018Date of Patent: February 4, 2020Assignee: Renesas Electronics CorporationInventors: Takeshi Hashizume, Naoya Fujita, Shunya Nagata, Yoshisato Yokoyama, Katsumi Shinbo, Kouji Satou
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Patent number: 10490262Abstract: A semiconductor device includes a memory unit having a memory cell driven by a voltage applied from power supply lines VSS and VDD, and a memory unit potential controller for adjusting the potential of the voltage applied to the memory cell. The memory unit potential controller includes a first potential adjustment part provided between the power supply lines VSS and ARVSS, and a second potential adjustment part provided between the power supply lines VDD and ARVSS. Further, the memory unit potential controller adjusts the potential of the power supply line ARVSS based on a first current supplied between the power supply line VSS and a first end portion of the memory cell through the first potential adjustment part, and adjusts a second current supplied between the power supply lines VDD and ARVSS through the second potential adjustment part, in order to rapidly stabilize the potential applied to the memory cell.Type: GrantFiled: March 7, 2018Date of Patent: November 26, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshisato Yokoyama, Takeshi Hashizume, Toshiaki Sano
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Publication number: 20190355712Abstract: A semiconductor device includes a semiconductor substrate, a memory cell formed on the semiconductor substrate, a word line connected to the memory cell, and an auxiliary line connected to the word line.Type: ApplicationFiled: July 31, 2019Publication date: November 21, 2019Inventors: Yuta YOSHIDA, Makoto YABUUCHI, Yoshisato YOKOYAMA
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Publication number: 20190296734Abstract: A MOS transistor is allowed to recover from BTI degradation even when an operation mode signal is inactive. A semiconductor device includes a drive circuit coupled to a controlled circuit via a delay element. The drive circuit includes first and second MOS transistors coupled in series to each other. The first MOS transistor is controlled to be in an OFF state when the operation mode signal is active. When the operation mode signal is inactive, the first MOS transistor is controlled to be in the OFF state at least temporarily while the second MOS transistor is controlled to be in the OFF.Type: ApplicationFiled: February 26, 2019Publication date: September 26, 2019Inventors: Yoshisato YOKOYAMA, Toshiaki SANO
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Publication number: 20190293716Abstract: A semiconductor device includes a memory cell array, a plurality of word lines, a plurality of bit line pairs, a column selection circuit coupling a bit line pair in a selected column in the plurality of bit line pairs to first and second output signal lines on the basis of a column selection signal, and a sense amplifier amplifying the voltage difference between the first and second output signal lines. The semiconductor device further includes: a scan flip flop to which the data can be input via a scan chain; and a voltage setting circuit setting the first and second output signal lines to voltage according to the data held in the scan flip flop in a scan test.Type: ApplicationFiled: February 26, 2019Publication date: September 26, 2019Inventor: Yoshisato YOKOYAMA
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Patent number: 10424575Abstract: Based on a basic idea to effectively utilize a space created in a third wiring layer (M3) by a zero-th wiring layer (M0) which can exist by miniaturization of a FINFET, an auxiliary line AL is arranged in the space created in the third wiring layer, and this auxiliary line AL and a word line WL are electrically connected to each other. Thus, a measure (device) based on such new knowledge that rising time of a word line voltage is largely affected by a wiring resistance of the word line is achieved, a high-speed operation in an SRAM using the FINFET is achieved.Type: GrantFiled: March 26, 2015Date of Patent: September 24, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yuta Yoshida, Makoto Yabuuchi, Yoshisato Yokoyama
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Patent number: 10373675Abstract: A semiconductor storage device includes, a memory array, a plurality of memory cells provided in rows and columns, and a control circuit for controlling the memory array, each of the memory cells being a static-type memory cell comprising driving transistors, transfer transistors, and load elements.Type: GrantFiled: April 20, 2017Date of Patent: August 6, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshisato Yokoyama, Yuichiro Ishii
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Publication number: 20180349222Abstract: A selection decoder controls levels of a plurality of selection signals based on an address bit having at least one or more bits. A memory module is selected when its corresponding selection signal is at an activated level, and data can be read and written therein. A failure determination unit determines whether or not the selection decoder is in a failed state based on the levels of the plurality of selection signals.Type: ApplicationFiled: May 21, 2018Publication date: December 6, 2018Applicant: Renesas Electronics CorporationInventors: Takeshi HASHIZUME, Naoya FUJITA, Shunya NAGATA, Yoshisato YOKOYAMA, Katsumi SHINBO, Kouji SATOU
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Publication number: 20180315470Abstract: A semiconductor device includes a memory unit having a memory cell driven by a voltage applied from power supply lines VSS and VDD, and a memory unit potential controller for adjusting the potential of the voltage applied to the memory cell. The memory unit potential controller includes a first potential adjustment part provided between the power supply lines VSS and ARVSS, and a second potential adjustment part provided between the power supply lines VDD and ARVSS. Further, the memory unit potential controller adjusts the potential of the power supply line ARVSS based on a first current supplied between the power supply line VSS and a first end portion of the memory cell through the first potential adjustment part, and adjusts a second current supplied between the power supply lines VDD and ARVSS through the second potential adjustment part, in order to rapidly stabilize the potential applied to the memory cell.Type: ApplicationFiled: March 7, 2018Publication date: November 1, 2018Inventors: Yoshisato YOKOYAMA, Takeshi HASHIZUME, Toshiaki SANO
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Patent number: 10109337Abstract: Provided is a memory macro which allows detection of a fault in a fetch circuit for an address signal which is input. The memory micro includes an address input terminal, a clock input terminal, a memory array and a control unit. The control unit includes a temporary memory circuit which fetches an input address signal which is input into the address input terminal in synchronization with an input clock signal which is input from the clock input terminal and outputs the input address signal as an internal address signal. The memory macro further includes an internal address output terminal which outputs the internal address signal for comparison with the input address signal.Type: GrantFiled: June 5, 2017Date of Patent: October 23, 2018Assignee: Renesas Electronics CorporationInventors: Yoshisato Yokoyama, Yoshikazu Saito, Shunya Nagata, Toshiaki Sano, Takeshi Hashizume