Patents by Inventor Yoshitaka Aiba
Yoshitaka Aiba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9076789Abstract: A semiconductor device is disclosed that includes a support substrate, a first semiconductor element that is mounted on one side of the support substrate, a second semiconductor element including a high frequency electrode that is mounted on the one side of the support substrate, a via hole that is provided at the support substrate in relation to the high frequency electrode, and an external connection electrode that is provided on the other side of the support substrate in relation to the via hole.Type: GrantFiled: January 6, 2014Date of Patent: July 7, 2015Assignee: SOCIONEXT INC.Inventors: Yoshitaka Aiba, Tetsuya Fujisawa, Yoshiyuki Yoneda
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Publication number: 20140117562Abstract: A semiconductor device is disclosed that includes a support substrate, a first semiconductor element that is mounted on one side of the support substrate, a second semiconductor element including a high frequency electrode that is mounted on the one side of the support substrate, a via hole that is provided at the support substrate in relation to the high frequency electrode, and an external connection electrode that is provided on the other side of the support substrate in relation to the via hole.Type: ApplicationFiled: January 6, 2014Publication date: May 1, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Yoshitaka Aiba, Tetsuya Fujisawa, Yoshiyuki Yoneda
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Patent number: 8344490Abstract: A semiconductor device is disclosed that includes a support substrate, a first semiconductor element that is mounted on one side of the support substrate, a second semiconductor element including a high frequency electrode that is mounted on the one side of the support substrate, a via hole that is provided at the support substrate in relation to the high frequency electrode, and an external connection electrode that is provided on the other side of the support substrate in relation to the via hole.Type: GrantFiled: March 13, 2008Date of Patent: January 1, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Yoshitaka Aiba, Tetsuya Fujisawa, Yoshiyuki Yonoda
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Patent number: 8324714Abstract: A semiconductor device includes a semiconductor substrate having a main surface in which a semiconductor element region where a plurality of functional elements are formed is formed; a multilevel wiring layer disposed on the main surface of the semiconductor substrate; a first organic insulating material layer disposed on the multilevel wiring layer; a groove that penetrates the multilevel wiring layer on a scribe region that surrounds the semiconductor element region; and an organic insulating material that is spaced from the first organic insulating material layer and disposed in the groove.Type: GrantFiled: November 30, 2010Date of Patent: December 4, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Jun Tsukakoshi, Yoshitaka Aiba
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Publication number: 20110127647Abstract: A semiconductor device includes a semiconductor substrate having a main surface in which a semiconductor element region where a plurality of functional elements are formed is formed; a multilevel wiring layer disposed on the main surface of the semiconductor substrate; a first organic insulating material layer disposed on the multilevel wiring layer; a groove that penetrates the multilevel wiring layer on a scribe region that surrounds the semiconductor element region; and an organic insulating material that is spaced from the first organic insulating material layer and disposed in the groove.Type: ApplicationFiled: November 30, 2010Publication date: June 2, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Jun TSUKAKOSHI, Yoshitaka AIBA
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Semiconductor device having a plurality of semiconductor chips and method for manufacturing the same
Patent number: 7759246Abstract: A semiconductor device includes a first semiconductor chip (5) having a first terminal (7) on one surface, a second semiconductor chip (1a) which is larger than the first semiconductor chip (5) and on which the first semiconductor chip (5) is stacked and which has a second terminal (3) on one surface, an insulating layer (10) formed on a second semiconductor chip (1a) to cover the first semiconductor chip (5), a plurality of holes (10a) formed in the insulating layer (10) on at least a peripheral area of the first semiconductor chip (5), a via (11a) formed like a film on inner peripheral surfaces and bottom surfaces of the holes (10a) and connected electrically to the second terminal (3) of the second semiconductor chip (1a), a wiring pattern (11b) formed on an upper surface of the insulating layer (10), and an external terminal (14) formed on the wiring pattern (11b).Type: GrantFiled: June 30, 2006Date of Patent: July 20, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Hirohisa Matsuki, Yoshitaka Aiba, Mitsutaka Sato, Tadahiro Okamato -
Patent number: 7602055Abstract: A semiconductor device with a WLP structure that enables the improvement of heat resistance. A dam layer which spreads over a PI film and an Si substrate for a chip is formed between the Si substrate and a sealing resin so as to surround the chip on all sides. A material for the dam layer is selected so that good adhesion will be obtained between the dam layer and the Si substrate, between the dam layer and the PI film, and between the dam layer and the sealing resin. As a result, even if a crack appears at a portion on a side of the semiconductor device where the Si substrate and the sealed resin are joined in a heating environment, the crack does not run inside the dam layer. This prevents the peeling of the sealing resin or peeling inside the chip and the performance of the semiconductor device is maintained.Type: GrantFiled: March 28, 2006Date of Patent: October 13, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Keiji Nosaka, Yoshitaka Aiba
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Patent number: 7456089Abstract: A semiconductor device comprises a semiconductor chip, a wiring layer formed on the semiconductor chip, a column electrode connected at a first end to the wiring layer, and an encapsulation resin formed on the semiconductor chip. In the semiconductor device, the column electrode is provided with a second end, opposite to the first end, projecting from the encapsulation resin, and an external connection member is connected to the column electrode at the second end so that the external connection member is separate from a surface of the encapsulation resin.Type: GrantFiled: August 30, 2006Date of Patent: November 25, 2008Assignee: Fujitsu LimitedInventors: Yoshitaka Aiba, Ryuji Nomoto
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Publication number: 20080197466Abstract: A semiconductor device includes: a semiconductor chip; a plurality of pellet-like electrically conductive members connected to electrodes of the semiconductor chip; and an encapsulation resin that encapsulates the semiconductor chip and the electrically conductive members. The electrically conductive members are embedded into the encapsulation resin. Surfaces of the electrically conductive members are exposed from the encapsulation resin so that the electrically conductive members serve as external connection terminals of the semiconductor device.Type: ApplicationFiled: April 29, 2008Publication date: August 21, 2008Applicant: FUJITSU LIMITEDInventors: Ryuji NOMOTO, Yoshitaka AIBA
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Publication number: 20080174001Abstract: A semiconductor device is disclosed that includes a support substrate, a first semiconductor element that is mounted on one side of the support substrate, a second semiconductor element including a high frequency electrode that is mounted on the one side of the support substrate, a via hole that is provided at the support substrate in relation to the high frequency electrode, and an external connection electrode that is provided on the other side of the support substrate in relation to the via hole.Type: ApplicationFiled: March 13, 2008Publication date: July 24, 2008Applicant: FUJITSU LIMITEDInventors: Yoshitaka Aiba, Tetsuya Fujisawa, Yoshiyuki Yoneda
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Patent number: 7365434Abstract: To provide a semiconductor device with high performance and reliability, in which peeling off an interconnection layer caused due to peeling off of a resin film at a land part is suppressed and thus electrical break down is prevented, and an efficient method for manufacturing the semiconductor device. The semiconductor device includes a semiconductor substrate (e.g., a silicon wafer 10); an insulating film 12 formed on the semiconductor substrate 10; a conductive layer 20 formed on the insulating film 12, the conductive layer 20 formed of an interconnection part 22 and a land part 24 which connects the interconnection part 22 to an external terminal 40; and a resin film 30 covering the conductive layer 20, wherein the resin film 30 is in contact with the insulating film 12 at least at a part of the land part 24 by passing through the conductive layer 20.Type: GrantFiled: May 26, 2006Date of Patent: April 29, 2008Assignee: Fujitsu LimitedInventor: Yoshitaka Aiba
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Publication number: 20070249093Abstract: A semiconductor device comprises a semiconductor chip, a wiring layer formed on the semiconductor chip, a column electrode connected at a first end to the wiring layer, and an encapsulation resin formed on the semiconductor chip. In the semiconductor device, the column electrode is provided with a second end, opposite to the first end, projecting from the encapsulation resin, and an external connection member is connected to the column electrode at the second end so that the external connection member is separate from a surface of the encapsulation resin.Type: ApplicationFiled: August 30, 2006Publication date: October 25, 2007Applicant: FUJITSU LIMITEDInventors: Yoshitaka Aiba, Ryuji Nomoto
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Publication number: 20070194445Abstract: To provide a semiconductor device with high performance and reliability, in which peeling off an interconnection layer caused due to peeling off of a resin film at a land part is suppressed and thus electrical break down is prevented, and an efficient method for manufacturing the semiconductor device. The semiconductor device includes a semiconductor substrate (e.g., a silicon wafer 10); an insulating film 12 formed on the semiconductor substrate 10; a conductive layer 20 formed on the insulating film 12, the conductive layer 20 formed of an interconnection part 22 and a land part 24 which connects the interconnection part 22 to an external terminal 40; and a resin film 30 covering the conductive layer 20, wherein the resin film 30 is in contact with the insulating film 12 at least at a part of the land part 24 by passing through the conductive layer 20.Type: ApplicationFiled: May 26, 2006Publication date: August 23, 2007Applicant: FUJITSU LIMITEDInventor: Yoshitaka Aiba
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Patent number: 7251801Abstract: A method of design of a circuit board enabling high density conductor lines to be drawn efficiently. A rats nest is formed by connecting pads to which terminals of an electronic device are connected and external connection terminals by lines. A region with the highest density of lines of the rats nest is then selected and design rules relating to routes and dimensions of conductor lines are set in the region with the highest density of lines of the rats nest. Conductor lines are then laid at the region with the highest density of lines of the rats nest, and whether or not the conductor lines can be laid at the region with the highest density of lines of the rats nest is confirmed. Setting of the design rules and laying of conductor lines are if the conductor lines cannot be laid, and the conductor lines of the remaining regions are laid by the set design rules if the conductor lines can be laid.Type: GrantFiled: December 23, 2004Date of Patent: July 31, 2007Assignee: Fujitsu LimitedInventors: Kaname Ozawa, Mitsutaka Sato, Tetsuya Fujisawa, Yoshiyuki Yoneda, Ryuji Nomoto, Yoshitaka Aiba
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Publication number: 20070134843Abstract: A semiconductor device with a WLP structure that enables the improvement of heat resistance. A dam layer which spreads over a PI film and an Si substrate for a chip is formed between the Si substrate and a sealing resin so as to surround the chip on all sides. A material for the dam layer is selected so that good adhesion will be obtained between the dam layer and the Si substrate, between the dam layer and the PI film, and between the dam layer and the sealing resin. As a result, even if a crack appears at a portion on a side of the semiconductor device where the Si substrate and the sealed resin are joined in a heating environment, the crack does not run inside the dam layer. This prevents the peeling of the sealing resin or peeling inside the chip and the performance of the semiconductor device is maintained.Type: ApplicationFiled: March 28, 2006Publication date: June 14, 2007Applicant: FUJITSU LIMITEDInventors: Keiji Nosaka, Yoshitaka Aiba
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Semiconductor device having a plurality of semiconductor chips and method for manufacturing the same
Publication number: 20060246623Abstract: A semiconductor device includes a first semiconductor chip (5) having a first terminal (7) on one surface, a second semiconductor chip (1a) which is larger than the first semiconductor chip (5) and on which the first semiconductor chip (5) is stacked and which has a second terminal (3) on one surface, an insulating layer (10) formed on a second semiconductor chip (1a) to cover the first semiconductor chip (5), a plurality of holes (10a) formed in the insulating layer (10) on at least a peripheral area of the first semiconductor chip (5), a via (11a) formed like a film on inner peripheral surfaces and bottom surfaces of the holes (10a) and connected electrically to the second terminal (3) of the second semiconductor chip (1a), a wiring pattern (11b) formed on an upper surface of the insulating layer (10), and an external terminal (14) formed on the wiring pattern (11b).Type: ApplicationFiled: June 30, 2006Publication date: November 2, 2006Applicant: FUJITSU LIMITEDInventors: Hirohisa Matsuki, Yoshitaka Aiba, Mitsutaka Sato, Tadahiro Okamato -
Patent number: 7122897Abstract: A semiconductor device comprises a semiconductor chip, a wiring layer formed on the semiconductor chip, a column electrode connected at a first end to the wiring layer, and an encapsulation resin formed on the semiconductor chip. In the semiconductor device, the column electrode is provided with a second end, opposite to the first end, projecting from the encapsulation resin, and an external connection member is connected to the column electrode at the second end so that the external connection member is separate from a surface of the encapsulation resin.Type: GrantFiled: September 21, 2004Date of Patent: October 17, 2006Assignee: Fujitsu LimitedInventors: Yoshitaka Aiba, Ryuji Nomoto
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Publication number: 20060186524Abstract: A semiconductor device is disclosed that includes a support substrate, a first semiconductor element that is mounted on one side of the support substrate, a second semiconductor element including a high frequency electrode that is mounted on the one side of the support substrate, a via hole that is provided at the support substrate in relation to the high frequency electrode, and an external connection electrode that is provided on the other side of the support substrate in relation to the via hole.Type: ApplicationFiled: May 25, 2005Publication date: August 24, 2006Applicant: FUJITSU LIMITEDInventors: Yoshitaka Aiba, Tetsuya Fujisawa, Yoshiyuki Yoneda
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Semiconductor device having a plurality of semiconductor chips and method for manufacturing the same
Patent number: 7084513Abstract: A semiconductor device includes a first semiconductor chip (5) having a first terminal (7) on one surface, a second semiconductor chip (1a) which is larger than the first semiconductor chip (5) and on which the first semiconductor chip (5) is stacked and which has a second terminal (3) on one surface, an insulating layer (10) formed on a second semiconductor chip (1a) to cover the first semiconductor chip (5), a plurality of holes (10a) formed in the insulating layer (10) on at least a peripheral area of the first semiconductor chip (5), a via (11a) formed like a film on inner peripheral surfaces and bottom surfaces of the holes (10a) and connected electrically to the second terminal (3) of the second semiconductor chip (1a), a wiring pattern (11b) formed on an upper surface of the insulating layer (10), and an external terminal (14) formed on the wiring pattern (11b).Type: GrantFiled: June 4, 2004Date of Patent: August 1, 2006Assignee: Fujitsu LimitedInventors: Hirohisa Matsuki, Yoshitaka Aiba, Mitsutaka Sato, Tadahiro Okamato -
Publication number: 20060040532Abstract: A method of design of a circuit board enabling high density conductor lines to be drawn efficiently. A rats nest is formed by connecting pads to which terminals of an electronic device are connected and external connection terminals by lines. A region with the highest density of lines of the rats nest is then selected and design rules relating to routes and dimensions of conductor lines are set in the region with the highest density of lines of the rats nest. Conductor lines are then laid at the region with the highest density of lines of the rats nest, and whether or not the conductor lines can be laid at the region with the highest density of lines of the rats nest is confirmed. Setting of the design rules and laying of conductor lines are if the conductor lines cannot be laid, and the conductor lines of the remaining regions are laid by the set design rules if the conductor lines can be laid.Type: ApplicationFiled: December 23, 2004Publication date: February 23, 2006Applicant: FUJITSU LIMITEDInventors: Kaname Ozawa, Mitsutaka Sato, Tetsuya Fujisawa, Yoshiyuki Yoneda, Ryuji Nomoto, Yoshitaka Aiba