Patents by Inventor Yoshitaka Matsuoka
Yoshitaka Matsuoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7701282Abstract: An offset canceling circuit includes a differential amplifier circuit configured to output a first output signal in response to a differential input signal; a latch circuit configured to hold a second output signal determined based on the first output signal; and an offset control circuit configured to supply a reference voltage to the differential amplifier circuit to adjust an offset of the differential amplifier circuit. The second output signal is a binary signal, and the latch circuit changes a signal level of the second output signal based on the first output signal. The offset control circuit acquires the second output signal from the latch circuit for every predetermined time and updates a voltage value of the reference voltage based on the signal levels of two of the second output signals which are acquired continuously in time series.Type: GrantFiled: March 31, 2008Date of Patent: April 20, 2010Assignee: NEC CorporationInventor: Yoshitaka Matsuoka
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Patent number: 7622964Abstract: An analog buffer circuit (10) includes a first p channel field effect transistor (11), an n channel field effect transistor (12) and a second p channel field effect transistor (13). The transistors are connected to one another in serial between power supplying terminals (VDD and GND). The transistors have gates connected to an input terminal (IN) in common. An output terminal (OUT) is connected to a connecting point between the n channel transistor and the second p channel transistor. With this structure, output voltage which appears on the output terminal is approximately proportional to input voltage supplied to the input terminal.Type: GrantFiled: March 23, 2006Date of Patent: November 24, 2009Assignee: NEC CorporationInventor: Yoshitaka Matsuoka
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Publication number: 20080238547Abstract: An offset canceling circuit includes a differential amplifier circuit configured to output a first output signal in response to a differential input signal; a latch circuit configured to hold a second output signal determined based on the first output signal; and an offset control circuit configured to supply a reference voltage to the differential amplifier circuit to adjust an offset of the differential amplifier circuit. The second output signal is a binary signal, and the latch circuit changes a signal level of the second output signal based on the first output signal. The offset control circuit acquires the second output signal from the latch circuit for every predetermined time and updates a voltage value of the reference voltage based on the signal levels of two of the second output signals which are acquired continuously in time series.Type: ApplicationFiled: March 31, 2008Publication date: October 2, 2008Inventor: Yoshitaka MATSUOKA
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Patent number: 7285998Abstract: A duty ratio adjusting circuit has a differential buffer (11) to produce a pulse signal (Dout) according to an input sine wave signal (Ain) and a reference voltage. The pulse signal is inverted and filtered to be supplied to a first analog buffer (14) as a direct voltage. The first analog buffer outputs voltage equal to the direct voltage. A second analog buffer (15) has the same structure as the first analog buffer and outputs voltage equal to the reference voltage. A differential amplifying circuit (16) produces an output voltage (SDout) as the reference voltage according to the difference between voltages output from the first and the second analog buffers. Capacitor (17, 19) connected to lines connecting between the first and the second analog buffers and the differential amplifying circuit.Type: GrantFiled: March 23, 2006Date of Patent: October 23, 2007Assignee: NEC CorporationInventor: Yoshitaka Matsuoka
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Publication number: 20060214713Abstract: A duty ratio adjusting circuit has a differential buffer (11) to produce a pulse signal (Dout) according to an input sine wave signal (Ain) and a reference voltage. The pulse signal is inverted and filtered to be supplied to a first analog buffer (14) as a direct voltage. The first analog buffer outputs voltage equal to the direct voltage. A second analog buffer (15) has the same structure as the first analog buffer and outputs voltage equal to the reference voltage. A differential amplifying circuit (16) produces an output voltage (SDout) as the reference voltage according to the difference between voltages output from the first and the second analog buffers. Capacitor (17,19) connected to lines connecting between the first and the second analog buffers and the differential amplifying circuit.Type: ApplicationFiled: March 23, 2006Publication date: September 28, 2006Applicant: NEC CorporationInventor: Yoshitaka Matsuoka
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Publication number: 20060214703Abstract: An analog buffer circuit (10) includes a first p channel field effect transistor (11), an n channel field effect transistor (12) and a second p channel field effect transistor (13). The transistors are connected to one another in serial between power supplying terminals (VDD and GND). The transistors have gates connected to an input terminal (IN) in common. An output terminal (OUT) is connected to a connecting point between the n channel transistor and the second p channel transistor. With this structure, output voltage which appears on the output terminal is approximately proportional to input voltage supplied to the input terminal.Type: ApplicationFiled: March 23, 2006Publication date: September 28, 2006Inventor: Yoshitaka Matsuoka
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Patent number: 4618844Abstract: In a semiconductor pressure transducer in accordance with the present invention, an oxide film is formed on a semiconductor base having a strain gauge resistor element for the purpose of protecting the strain gauge resistor element. Over the oxide film, a conductive metal film is formed which does not overlap with the strain gauge resistor element through said oxide film.Type: GrantFiled: May 12, 1983Date of Patent: October 21, 1986Assignee: Hitachi, Ltd.Inventors: Yukio Takahashi, Michitaka Shimazoe, Yoshitaka Matsuoka
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Patent number: 4454771Abstract: A load cell comprises a semiconductor diaphragm which includes an outer flange portion, a central rigid portion having a smaller thickness than the outer flange portion and a thin resilient portion provided between the outer flange portion and the central rigid portion. At least two piezo-resistors constituting at least part of a bridge circuit are formed in the resilient portion. The load cell further comprises a first glass block secured to the central rigid portion, and a second glass block for securing the outer flange portion. A load is applied to the semiconductor diaphragm through the first glass block, wherein measurement of the applied load is effected by detecting variation in resistance of the resistor bridge circuit.Type: GrantFiled: November 5, 1981Date of Patent: June 19, 1984Assignee: Hitachi, Ltd.Inventors: Michitaka Shimazoe, Yoshitaka Matsuoka
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Patent number: 4364276Abstract: A differential pressure measuring transducer assembly including a measuring diaphragm formed of semiconductor material having gauge resistance elements on one surface thereof and a central boss area of large thickness and a peripheral support flange on the other surface thereof defining therebetween an annular portion of small thickness. The measuring diaphragm is attached at the peripheral support flange to a glass support member and a metallic support member formed with pressure conducting bores respectively communicating with each other. The metallic support member is formed of material having a Young's modulus substantially equal to that of the measuring diaphragm.Type: GrantFiled: December 16, 1980Date of Patent: December 21, 1982Assignee: Hitachi, Ltd.Inventors: Michitaka Shimazoe, Yoshitaka Matsuoka, Ryozo Akahane, Yasushi Shimizu, Hideyuki Nemoto, Masanori Tanabe
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Patent number: 4342231Abstract: A differential pressure transmitter has a pressure receiving portion and a sensor portion which are constituted from separate parts separably jointed with each other. The sensor portion includes a semiconductor sensor having one side formed with a resistance pattern and the other side which has a thick-walled peripheral portion and a thick-walled central portion. The semiconductor sensor is incorporated in the sensor portion as being supported at the thick-walled peripheral portion thereof. The pressure receiving portion includes seal diaphragms disposed on both sides of the pressure receiving portion and a central diaphragm disposed therein. The semiconductor sensor is arranged such that the side thereof carrying the resistance pattern faces the pressure receiving portion.Type: GrantFiled: December 16, 1980Date of Patent: August 3, 1982Assignee: Hitachi, Ltd.Inventors: Yoshimi Yamamoto, Yoshitaka Matsuoka, Syozo Kasai, Yukio Takahashi, Takeo Nagata, Akira Nagasu, Tomomasa Yoshida, Satoshi Shimada
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Patent number: 4306460Abstract: A differential pressure transducer having a cantilever and a semiconductor strain gauge attached to each side of the cantilever at an intermediate portion of the latter. The cantilever has one end fixed by electron beam welding to a fixing member and the other end left for free displacement in response to a differential pressure. The displacement of the other end of the cantilever is detected as changes in the electric resistances of the semiconductor strain gauges.Type: GrantFiled: December 13, 1979Date of Patent: December 22, 1981Assignee: Hitachi, Ltd.Inventors: Yutaka Sakurai, Takeo Nagata, Yoshitaka Matsuoka, Satoshi Shimada, Mitsuo Ai
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Patent number: 4303903Abstract: A pressure transducer comprising a silicon diaphragm on which a semiconductor strain gauge is formed and which has a diaphragm portion deformable in response to a pressure, an insulating support which is made of borosilicate glass having the silicon diaphragm rigidly mounted thereon and which is provided with a pressure introducing hole in its central part, a metallic support which is cylindrical, which is made of an iron-nickel alloy similar in the thermal expansion coefficient to the borosilicate glass and on which the glass insulating support is rigidly mounted, and a metallic housing within which the integrated structure consisting of the silicon diaphragm, the glass insulating support and the metallic support is arranged; the silicon diaphragm, the insulating support and the metallic support being joined by the anodic bonding, the metallic support being rigidly welded to the metallic housing at its lower end part.Type: GrantFiled: September 21, 1979Date of Patent: December 1, 1981Assignee: Hitachi, Ltd.Inventors: Yoshitaka Matsuoka, Michitaka Shimazoe, Yoshimi Yamamoto, Mitsuo Ai, Keiji Miyauchi, Hideyuki Nemoto, Masatoshi Tsuchiya, Masanori Tanabe
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Patent number: 4264889Abstract: A pressure transducer has at least one pressure transmitting space filled with liquid, a space for a pressure to be sensed connected to the pressure transmitting space through a diaphragm, and a pressure sensitive element in the pressure transmitting space for transducing a pressure transmitted from the space for the pressure to be sensed to the pressure transmitting space through the diaphragm to an electrical signal. A printed circuit board wired to electrically connect terminals of the pressure sensitive element is arranged closely to the element and thin temperature sensitive elements for temperature-compensating the pressure sensitive element are arranged on the printed circuit board.Type: GrantFiled: January 18, 1980Date of Patent: April 28, 1981Assignee: Hitachi, Ltd.Inventors: Yoshimi Yamamoto, Mitsuo Ai, Yoshitaka Matsuoka, Takeo Nagata, Tsutomu Okayama, Akira Ikegami
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Patent number: 4173900Abstract: A semiconductor pressure transducer comprising a disc-shaped pressure-responsive diaphragm; a pair of radial strain gauge units having a piezoresistance effect, formed by injecting an impurity in the radial direction in the surface of the diaphragm; and a pair of tangential strain gauge units having a piezoresistance effect, formed by injecting an impurity in the tangential direction in the surface of the diaphragm, wherein the distance from the pair of the radial strain gauge units to the center of the circular diaphragm is greater than the distance from the pair of the tangential strain gauge units to the center of the circular diaphragm.Type: GrantFiled: March 6, 1978Date of Patent: November 13, 1979Assignee: Hitachi, Ltd.Inventors: Masanori Tanabe, Satoshi Shimada, Motohisa Nishihara, Kazuji Yamada, Yasumasa Matsuda, Michitaka Shimazoe, Yoshitaka Matsuoka, Yukio Takahashi, Katsuya Katohgi, Mitsuo Ai
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Patent number: 4173148Abstract: A bridge circuit with four arms including semiconductor strain gauge elements has input terminals for coupling a DC power supply with a pair of diagonally opposite junctions of the bridge circuit per se and output terminals coupled with a pair of remaining diagonally opposite junctions. Initial zero-point temperature compensators each are connected in series and in parallel to each of semiconductor strain gauge elements on adjacent two arms of the bridge circuit. Temperature compensators for zero-point shift adjustment are each provided between the adjacent arms closer to each output terminal. A temperature compensator for span adjustment is provided between one of the input terminals and the DC power source. A constant current control unit for feeding a constant current to the bridge circuit is provided between the other input terminal and the DC power supply.Type: GrantFiled: October 5, 1978Date of Patent: November 6, 1979Assignee: Hitachi, LtdInventors: Kazuji Yamada, Hideo Sato, Tsutomu Okayama, Motohisa Nishihara, Yoshitaka Matsuoka, Katsuya Katohgi, Yasumasa Matsuda, Satoshi Shimada
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Patent number: 4166384Abstract: A semiconductor transducer comprising an improved strain-yielding body yielding a strain in response to the impartation of a force or displacement, and a semiconductor strain gauge bonded to the strain-yielding body. The improved strain-yielding body is made of an iron-nickel-cobalt alloy containing 28.2 to 31.0% by weight of nickel and 15.0 to 19.5% by weight of cobalt. This iron-nickel-cobalt alloy is initially heated up to a temperature above 600.degree. C. for the purpose of standard heat treatment for removing its internal strain. After the standard heat treatment, the iron-nickel-cobalt alloy is subjected to cold working at a working rate of more than and including 60%, and is then subjected to heat treatment at a temperature between 350.degree. C. and 600.degree. C. The heat-treated iron-nickel-cobalt alloy is shaped into the predetermined form of the strain-yielding body.Type: GrantFiled: September 6, 1978Date of Patent: September 4, 1979Assignee: Hitachi, Ltd.Inventors: Yasumasa Matsuda, Kazuji Yamada, Satoshi Shimada, Motohisa Nishihara, Tomio Yasuda, Masatoshi Tsuchiya, Ko Soeno, Mitsuo Ai, Takeo Nagata, Yoshitaka Matsuoka