Patents by Inventor Yoshitaka NAGASATO

Yoshitaka NAGASATO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230160104
    Abstract: A method for manufacturing a semiconductor device includes: preparing a processed wafer having a gallium nitride (GaN) wafer and an epitaxial layer on the GaN wafer; forming a device constituent part in a portion of the processes wafer adjacent to a front surface provided by the epitaxial layer; forming a modified layer inside of the processed wafer by applying a laser beam from a back surface side opposite to the front surface side: and dividing the processed wafer at the modified layer. The processed wafer prepared includes a reflective layer for reflecting the laser beam at a position separated from a planned formation position, where the modified layer is to be formed, by a predetermined distance toward the front surface side. The reflective layer contains a layer having a refractive index different from that of a GaN single crystal of an epitaxial layer.
    Type: Application
    Filed: November 16, 2022
    Publication date: May 25, 2023
    Inventors: Junji OHARA, Takashi ISHIDA, Yoshitaka NAGASATO, Daisuke KAWAGUCHI, Chiaki SASAOKA, Shoichi ONDA, Jun KOJIMA
  • Publication number: 20230116208
    Abstract: A method of manufacturing a semiconductor device includes a trench forming step, a laser irradiation step and a peeling step. In the trench forming step, a trench is formed on a first main surface of a semiconductor substrate having a device structure formed thereon. In the laser irradiation step, a laser is irradiated from a second main surface of the semiconductor substrate to a plane surface that is positioned and extends at a predetermined depth of the semiconductor substrate. In the peeling step, a device layer is peeled off from the semiconductor substrate along the plane surface on which the laser is irradiated. The peeling step may be performed in a state in which the trenches are either unfilled or filled with a material having a lower coefficient of thermal expansion than the semiconductor substrate.
    Type: Application
    Filed: October 6, 2022
    Publication date: April 13, 2023
    Inventors: TAKASHI USHIJIMA, KOZO KATO, YOSHITAKA NAGASATO, MASATAKE NAGAYA, SHINICHI HOSHI, DAISUKE KAWAGUCHI, KEISUKE HARA
  • Publication number: 20230081110
    Abstract: In a surface treatment method for a gallium oxide-based semiconductor substrate, a surface of the gallium oxide-based semiconductor substrate is flattened by dry etching with a self-bias of 150 V or more. After the surface of the gallium oxide-based semiconductor substrate is flattened, the surface of the gallium oxide-based semiconductor substrate is washed with a chemical solution containing H2SO4 to expose a step terrace structure on the surface of the gallium oxide-based semiconductor substrate.
    Type: Application
    Filed: August 18, 2022
    Publication date: March 16, 2023
    Inventors: KATSUHIRO KUTSUKI, KEITA KATAOKA, DAIGO KIKUTA, HIROKI MIYAKE, SHUHEI ICHIKAWA, YOSHITAKA NAGASATO
  • Patent number: 10680091
    Abstract: In a semiconductor device having a heterojunction type superjunction structure, a drain portion and a source portion are electrically connected to one of a two-dimensional electron gas layer and a two-dimensional hole gas layer, and a gate portion is prevented by an insulating region from directly contacting the one of the two-dimensional election gas layer and the two-dimensional hole gas layer.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: June 9, 2020
    Assignees: Toyota Jidosha Kabushiki Kaisha, Toyota School Foundation
    Inventors: Tomoyoshi Kushida, Yoshitaka Nagasato, Naotaka Iwata, Hiroyuki Sakaki
  • Publication number: 20190198652
    Abstract: In a semiconductor device having a heterojunction type superjunction structure, a drain portion and a source portion are electrically connected to one of a two-dimensional electron gas layer and a two-dimensional hole gas layer, and a gate portion is prevented by an insulating region from directly contacting the one of the two-dimensional election gas layer and the two-dimensional hole gas layer.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 27, 2019
    Applicants: Toyota Jidosha Kabushiki Kaisha, Toyota School Foundation
    Inventors: Tomoyoshi Kushida, Yoshitaka Nagasato, Naotaka Iwata, Hiroyuki Sakaki
  • Patent number: 10002863
    Abstract: A semiconductor device is capable of accurately sensing a temperature of a semiconductor element incorporated in a semiconductor substrate. The semiconductor device includes a temperature sensor. The temperature sensor includes a first nitride semiconductor layer of p-type, a first sense electrode, and a second sense electrode. The first sense electrode and the second sense electrode are located to be capable of passing an electric current between the first sense electrode and the second sense electrode through the first nitride semiconductor layer.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: June 19, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hidemoto Tomita, Yoshitaka Nagasato, Takashi Okawa, Masakazu Kanechika, Hiroyuki Ueda
  • Publication number: 20170154885
    Abstract: A nitride semiconductor device includes a conductive substrate and a nitride semiconductor layer. The nitride semiconductor layer is disposed on the conductive substrate. The nitride semiconductor layer includes a first transistor structure of a lateral type and a second transistor structure of a lateral type. The conductive substrate includes a first potential control region and a second potential control region capable of controlling potential independently from the first potential control region. In planar view of the nitride semiconductor layer, the first transistor structure overlaps the first potential control region and the second transistor structure overlaps the second potential control region.
    Type: Application
    Filed: October 12, 2016
    Publication date: June 1, 2017
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yoshitaka NAGASATO, Hidemoto TOMITA, Masakazu KANECHIKA
  • Patent number: 9666580
    Abstract: A nitride semiconductor device includes a conductive substrate and a nitride semiconductor layer. The nitride semiconductor layer is disposed on the conductive substrate. The nitride semiconductor layer includes a first transistor structure of a lateral type and a second transistor structure of a lateral type. The conductive substrate includes a first potential control region and a second potential control region capable of controlling potential independently from the first potential control region. In planar view of the nitride semiconductor layer, the first transistor structure overlaps the first potential control region and the second transistor structure overlaps the second potential control region.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: May 30, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yoshitaka Nagasato, Hidemoto Tomita, Masakazu Kanechika
  • Publication number: 20160343702
    Abstract: A semiconductor device is capable of accurately sensing a temperature of a semiconductor element incorporated in a semiconductor substrate. The semiconductor device includes a temperature sensor. The temperature sensor includes a first nitride semiconductor layer of p-type, a first sense electrode, and a second sense electrode. The first sense electrode and the second sense electrode are located to be capable of passing an electric current between the first sense electrode and the second sense electrode through the first nitride semiconductor layer.
    Type: Application
    Filed: May 3, 2016
    Publication date: November 24, 2016
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hidemoto TOMITA, Yoshitaka NAGASATO, Takashi OKAWA, Masakazu KANECHIKA, Hiroyuki UEDA