Patents by Inventor Yoshitaka Nishimura

Yoshitaka Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240033641
    Abstract: Provided is a game machine in which pieces of music prepared in a music distribution service provided only to members can be utilized in game play. A game machine provides a music selection opportunity to select music for play, such that multiple pieces of music are included as options in a music distribution service, which is provided separately from music games as a service that distributes multiple pieces of music only to user terminal devices that have passed member authentication. In addition, the game machine acquires musical score data for play corresponding to music for play from a game distribution system connected via a network. Furthermore, the game machine acquires music data corresponding to music for play from a music distribution system connected via the network, such that a music game is provided according to the combination of the music data and the musical score data for play.
    Type: Application
    Filed: October 13, 2023
    Publication date: February 1, 2024
    Applicant: KONAMI AMUSEMENT CO., LTD.
    Inventors: Naoyuki SATO, Yoshitaka Nishimura, Shinya Ishida, Yuto Nishino
  • Patent number: 11791668
    Abstract: It is aimed to provide a power supply device and a power supply system which enable consumers to freely choose electrical power and specify transmission sources when receiving electrical power, and enable parties involved in transactions (power supply side and power receiving side) to reliably and safely perform transmission between them. There are provided a power supply device and a power supply system. The power supply device includes a baseband unit that generates a power signal, a modulation processing unit that modulates the power signal generated by the baseband unit to impart a code thereto for specifying a transmission source of the power signal and generates a modulated signal that can be demodulated by a power receiving device, and a transmission unit that transmits the modulated signal generated by the modulation processing unit.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: October 17, 2023
    Assignees: KYOTO UNIVERSITY, MINNA-DENRYOKU, INC.
    Inventors: Ken Umeno, Eiji Oishi, Yoshitaka Nishimura
  • Publication number: 20220149670
    Abstract: It is aimed to provide a power supply device and a power supply system which enable consumers to freely choose electrical power and specify transmission sources when receiving electrical power, and enable parties involved in transactions (power supply side and power receiving side) to reliably and safely perform transmission between them. There are provided a power supply device and a power supply system. The power supply device includes a baseband unit that generates a power signal, a modulation processing unit that modulates the power signal generated by the baseband unit to impart a code thereto for specifying a transmission source of the power signal and generates a modulated signal that can be demodulated by a power receiving device, and a transmission unit that transmits the modulated signal generated by the modulation processing unit.
    Type: Application
    Filed: March 13, 2020
    Publication date: May 12, 2022
    Applicants: KYOTO UNIVERSITY, MINNA-DENRYOKU, INC.
    Inventors: Ken UMENO, Eiji OISHI, Yoshitaka NISHIMURA
  • Publication number: 20210407953
    Abstract: A lead-free solder has a heat resistance temperature which is high and a thermal conductive property which is not changed in a high temperature range. A semiconductor device includes a solder material containing more than 5.0% by mass and 10.0% by mass or less of Sb and 2.0 to 4.0% by mass of Ag, an element selected from the group consisting of: more than 0 and 1.0% by mass or less of Si, more than 0 and 0.1% by mass or less of V, 0.001 to 0.1% by mass of Ge, 0.001 to 0.1% by mass of P, and more than 0 and 1.2% by mass or less of Cu, and the remainder consisting of Sn and inevitable impurities. A bonding layer including the solder material, is formed between a semiconductor element and a substrate electrode or a lead frame.
    Type: Application
    Filed: September 14, 2021
    Publication date: December 30, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hirohiko WATANABE, Shunsuke SAITO, Yoshitaka NISHIMURA, Fumihiko MOMOSE
  • Patent number: 11145615
    Abstract: A lead-free solder has a heat resistance temperature which is high and a thermal conductive property which is not changed in a high temperature range. A semiconductor device includes a solder material containing more than 5.0% by mass and 10.0% by mass or less of Sb and 2.0 to 4.0% by mass of Ag, and the remainder consisting of Sn and inevitable impurities. A bonding layer including the solder material, is formed between a semiconductor element and a substrate electrode or a lead frame.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: October 12, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hirohiko Watanabe, Shunsuke Saito, Yoshitaka Nishimura, Fumihiko Momose
  • Patent number: 10896892
    Abstract: Provided is a wire bonding apparatus for electrically connecting an electrode and an aluminum alloy wire to each other by wire bonding. The apparatus includes a wire feeding device which feeds the wire. The wire has a diameter not less than 500 ?m and not greater than 600 ?m. The apparatus includes a heating device heats the wire to a temperature that is not lower than 50° C. and not higher than 100° C. The apparatus further includes a pressure device which presses the wire against the electrode. The apparatus further includes an ultrasonic wave generating device which generates an ultrasonic vibration that is applied to the wire that is pressed by the pressure device.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: January 19, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Fumihiko Momose, Takashi Saito, Kazumasa Kido, Yoshitaka Nishimura
  • Publication number: 20200303337
    Abstract: A lead-free solder has a heat resistance temperature which is high and a thermal conductive property which is not changed in a high temperature range. A semiconductor device includes a solder material containing more than 5.0% by mass and 10.0% by mass or less of Sb and 2.0 to 4.0% by mass of Ag, and the remainder consisting of Sn and inevitable impurities. A bonding layer including the solder material, is formed between a semiconductor element and a substrate electrode or a lead frame.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 24, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hirohiko WATANABE, Shunsuke SAITO, Yoshitaka NISHIMURA, Fumihiko MOMOSE
  • Patent number: 10727194
    Abstract: To provide a lead-free solder the heat resistance temperature of which is high and thermal conductive property of which are not changed in a high temperature range. A semiconductor device of the present invention includes a solder material containing more than 5.0% by mass and 10.0% by mass or less of Sb and 2.0 to 4.0% by mass of Ag, and the remainder consisting of Sn and inevitable impurities, and a bonding layer including the solder material, which is formed between a semiconductor element and a substrate electrode or a lead frame.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: July 28, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hirohiko Watanabe, Shunsuke Saito, Yoshitaka Nishimura, Fumihiko Momose
  • Patent number: 10446460
    Abstract: The semiconductor device includes a first insulating circuit substrate; a semiconductor chip including a plurality of control electrodes, disposed on the first insulating circuit substrate; a second insulating circuit substrate including a plurality of first through-holes in which conductive members are arranged on inner walls and/or an outer periphery of ends of the first through-holes, the second insulating circuit substrate being disposed above the semiconductor chips; and first pins inserted into the first through-holes and having at one end a columnar part connected to the control electrodes of the semiconductor chips, and having at another end a head part that is wider than an inner diameter of the first through-holes.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: October 15, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiromichi Gohara, Kohei Yamauchi, Shinji Tada, Tatsuo Nishizawa, Yoshitaka Nishimura
  • Patent number: 10322345
    Abstract: A game program product may include, but is not limited to: a non-transitory computer-readable medium, and a computer program stored in the non-transitory computer-readable medium. The computer program is, when executed by a computer of a game system, to cause the computer to at least: display at least: 1) a reference indicator at a position over a display screen; and 2) a moving object which moves toward the reference indicator on the display screen; change a position of a reference indicator displayed at a position over the display screen; receive an input of a user's operation; and determine success or failure of the user's operation, based at least in part on: a timing of receiving the input of the user's operation, and a timing that the moving object reaches the reference indicator.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: June 18, 2019
    Assignee: KONAMI DIGITAL ENTERTAINMENT CO., LTD.
    Inventors: Hiroaki Takahashi, Yoshitaka Nishimura
  • Patent number: 10322344
    Abstract: A game method is performed by one or more computers. The method may include, but is not limited to: displaying, on a display, 1) at least one reference indicator; 2) at least one target indicator; and 3) at least one operation indicator; recognizing, as the specific operation, a detected series of operations that an indictor gets contact with a predefined point of the detection area, before on the detection area the indicator slides while keeping the indicator in contact with the detection area; displaying, on the display, a guide indicator for guiding a slide-operational direction to which the indicator is operated to be slide; determining whether the specific operation responsive to the change of the cross position; and reflecting a result of the determination to a game result.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: June 18, 2019
    Assignee: KONAMI DIGITAL ENTERTAINMENT CO., LTD.
    Inventors: Yoshitaka Nishimura, Masahiro Kiyomoto
  • Patent number: 10297527
    Abstract: A semiconductor device includes a radiation plate having a rear surface roughened by a plurality of dents that overlap with each other; a laminated substrate provided on a front surface of the radiation plate and including an insulating plate, a circuit board provided on a front surface of the insulating plate, and a metal plate provided on a rear surface of the insulating plate; a semiconductor chip provided on the circuit board; a radiator; and a heat radiating material retained between the rear surface of the radiation plats and the radiator. The plurality of dents that roughen the rear surface of the radiation plate provides the rear surface with an arithmetic average roughness ranging from 1 ?m to 10 ?m, and each of the dents has a maximum dent depth ranging from 12 ?m to 71.5 ?m, and a dent width ranging from 0.17 mm to 0.72 mm.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: May 21, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi Saito, Fumihiko Momose, Yoshitaka Nishimura, Eiji Mochizuki
  • Patent number: 10276474
    Abstract: A semiconductor device includes a plurality of semiconductor elements; insulating circuit boards each including an insulating substrate, a circuit portion on a front surface of the insulating substrate connected to one semiconductor element, and a metal portion on a rear surface of the insulating substrate; a metal plate joined to the metal portions of the plurality of insulating circuit boards; and a joint member joining the plurality of insulating circuit boards to the metal plate. The metal plate has a front surface in which the insulating circuit boards are arranged apart from each other, and a rear surface including first regions corresponding to positions of the metal portions and second regions other than the first regions. At least a part of a surface of each of the first regions has a surface work-hardened layer, and the second regions have a hardness different from that of the surface work-hardened layer.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: April 30, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi Saito, Ryoichi Kato, Yoshitaka Nishimura, Fumihiko Momose
  • Patent number: 10157877
    Abstract: A solder joint layer has a structure in which plural fine-grained second crystal sections (22) precipitate at crystal grain boundaries between first crystal sections (21) dispersed in a matrix. The first crystal sections (21) are Sn crystal grains containing tin and antimony in a predetermined proportion. The second crystal sections (22) are made up of a first portion containing a predetermined proportion of Ag atoms with respect to Sn atoms, or a second portion containing a predetermined proportion of Cu atoms with respect to Sn atoms, or both. The solder joint layer may have third crystal sections (23) which are crystal grains that contain a predetermined proportion of Sb atoms with respect to Sn atoms. As a result, solder joining is enabled at a low melting point, and a highly reliable solder joint layer having a substantially uniform metal structure can be formed.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: December 18, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kazumasa Kido, Takashi Saitou, Kyouhei Fukuda, Shinji Tada, Fumihiko Momose, Yoshitaka Nishimura
  • Patent number: 10128166
    Abstract: A power semiconductor module includes a cooler; a plurality of power semiconductor units fixed on the cooler; and a bus bar unit connected electrically to the plurality of power semiconductor units. Each of the plurality of power semiconductor units includes a multilayered substrate including a circuit plate, an insulating plate, and a metal plate laminated in respective order; a semiconductor element fixed to the circuit plate; a wiring member having a printed circuit board and a plurality of conductive posts; external terminals connected electrically and mechanically to the circuit plate; and an insulating sealing material. The bus bar unit includes a plurality of bus bars mutually connecting the external terminals of the plurality of power semiconductor units.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: November 13, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Motohito Hori, Yoshikazu Takahashi, Eiji Mochizuki, Yoshitaka Nishimura, Yoshinari Ikeda
  • Patent number: 10128167
    Abstract: A semiconductor module is provided, including: a cooling-target device; a first cooling unit on which the cooling-target device is placed and that has a flow channel through which a refrigerant for cooling the cooling-target device flows; and a second cooling unit to which the first cooling unit is fixed and that has a flow channel coupled with the flow channel of the first cooling unit. Also, a semiconductor module manufacturing method is provided, including: placing a cooling-target device on a first cooling unit that has a flow channel through which a refrigerant for cooling the cooling-target device flows; and fixing the first cooling unit to a second cooling unit that has a flow channel coupled with the flow channel of the first cooling unit.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: November 13, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Akira Morozumi, Hiromichi Gohara, Yoshitaka Nishimura
  • Patent number: 10128345
    Abstract: A semiconductor device including a semiconductor element, an upper-surface electrode provided on an upper surface of the semiconductor element, a plated layer provided on an upper surface of the upper-surface electrode, one or more gate runners penetrating the plated layer and provided to extend in a predetermined direction on the upper surface of the semiconductor element, and a metal connecting plate that is arranged above the plated layer and is electrically connected to the upper-surface electrode, wherein the metal connecting plate has a joint portion parallel to the upper surface of the semiconductor element and has a rising portion that is connected to a first end of the joint portion and extends in a direction away from the upper surface of the semiconductor element, and in a plane parallel to the upper surface of the semiconductor element, the rising portion and the gate runner do not overlap with each other.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: November 13, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Hiromichi Gohara, Takafumi Yamada, Kohei Yamauchi, Tatsuhiko Asai, Yoshitaka Nishimura, Akio Kitamura, Hajime Masubuchi, Souichi Yoshida
  • Patent number: 10118094
    Abstract: Provided is a game machine which can actualize a play between games having different difficulty levels. The game machine is applied to a game system that progresses a game between game machines connected via a network. The game machine comprises an external storage that stores sequence data wherein each operation timing is written so as to differ from each other. And, the game machine: teaches each operation timing, based on sequence data that differs from sequence data used in another machine functioning as another terminal in the game system; obtains operation information for the other machine; and, based on it, determines whether or not prescribed reflection conditions have been fulfilled. Then, when the prescribed reflection conditions have been fulfilled based on its results, the game machine reflects the operation information for the other machine in a travel path for an object for teaching the operation timing for the game machine.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: November 6, 2018
    Assignee: KONAMI DIGITAL ENTERTAINMENT CO., LTD.
    Inventors: Yoshitaka Nishimura, Masahiro Kiyomoto, Shota Katagiri, Takao Yamamoto, Mayumi Okuyama, Tatsuya Iyama
  • Publication number: 20180315676
    Abstract: The semiconductor device includes a first insulating circuit substrate; a semiconductor chip including a plurality of control electrodes, disposed on the first insulating circuit substrate; a second insulating circuit substrate including a plurality of first through-holes in which conductive members are arranged on inner walls and/or an outer periphery of ends of the first through-holes, the second insulating circuit substrate being disposed above the semiconductor chips; and first pins inserted into the first through-holes and having at one end a columnar part connected to the control electrodes of the semiconductor chips, and having at another end a head part that is wider than an inner diameter of the first through-holes.
    Type: Application
    Filed: March 7, 2018
    Publication date: November 1, 2018
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Hiromichi GOHARA, Kohei YAMAUCHI, Shinji TADA, Tatsuo NISHIZAWA, Yoshitaka NISHIMURA
  • Patent number: 10090223
    Abstract: A semiconductor device includes a heat-dissipating base, a first conductive layer bonded to the top surface of the heat-dissipating base, an AlN insulating substrate bonded to the top surface of the first conductive layer, and an electrode terminal having one edge bending to form a bonding edge whose bottom surface faces the top surface of the second conductive layer and is solid-state bonded to a portion of the top surface of the second conductive layer. The crystal grain diameter at the bonded interface of the second conductive layer and electrode terminal is less than or equal to 1 ?m, and indentations from the ultrasonic horn are left in the top surface of the bonding edge.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: October 2, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Fumihiko Momose, Hiroyuki Nogawa, Yoshitaka Nishimura, Eiji Mochizuki