Abstract: A gunning transceiver logic input circuit is provided a construction, in which a high potential power source for a differential input circuit and a high potential power source for an internal CMOS circuit are mutually separated and independent of each other, upon performing an IDDQ test as a static current measuring test for an LSI including the differential input circuit flowing a steady-state current and an internal CMOS circuit not flowing the steady-state current. Upon IDDQ test, IDDQ test becomes possible to perform power supply from the power source independent from the power source of other CMOS circuit.

Abstract: A gunning transceiver logic input circuit is provided a construction, in which a high potential power source for a differential input circuit and a high potential power source for an internal CMOS circuit are mutually separated and independent of each other, upon performing an IDDQ test as a static current measuring test for an LSI including the differential input circuit flowing a steady-state current and an internal CMOS circuit not flowing the steady-state current. Upon IDDQ test, IDDQ test becomes possible to perform power supply from the power source independent from the power source of other CMOS circuit.

Abstract: A gunning transceiver logic input circuit is provided a construction, in which a high potential power source for a differential input circuit and a high potential power source for an internal CMOS circuit are mutually separated and independent of each other, upon performing an IDDQ test as a static current measuring test for an LSI including the differential input circuit flowing a steady-state current and an internal CMOS circuit not flowing the steady-state current. Upon IDDQ test, IDDQ test becomes possible to perform power supply from the power source independent from the power source of other CMOS circuit.

Abstract: An ECL output circuit comprises a current-switching type logic circuit formed by differentially connected first and second bipolar transistors whose common emitters are connected to a lower potential power supply, and an emitter follower circuit formed by a third bipolar transistor whose collector is connected to a higher potential power supply and whose base is connected to a collector of one of the first and second bipolar transistors. The ECL output circuit further comprises a first N-type MOS transistor having a source connected to the lower potential power supply, and a gate and a drain commonly connected to the higher potential power supply through a resistor and to a collector of the other one of the first and second bipolar transistors through a capacitor, and a second N-type MOS transistor having a gate connected to the gate of the first MOS transistor, a source connected to the lower potential power supply, and a drain connected to the emitter of the third bipolar transistor.

Abstract: An ECL-TTL level converter having a three-state output level is disclosed. A circuit provided in the converter for forming the three-state output level includes a function for protecting IC's connected to the output terminal of the converter when an negative power voltage applied to the converter is an abnormal condition.

Abstract: An ECL circuit includes a plurality of input terminals, a current source, a reference transistor having an emitter connected to the current source, a base receiving a reference voltage and a collector connected to a first resistor, a plurality of input transistors each having an emitter connected to the current source, a collector connected to a second resistor and a base connected to one of the input terminals, a plurality of pull-down resistors each connected between the base and the emitter of one of the input transistors, an emitter follower transistor having a base connected to the collector of the reference transistor or a common connection point of collectors of the input transistors and an emitter connected to an output terminal and a third resistor.

Abstract: A Schmitt trigger circuit comprising input and output terminals, first and second voltage supply lines, a first transistor having its base connected to the input terminal and its the collector connected to the first voltage supply line though a load resistor, a second transistor having its collector connected to the first voltage supply line, a first constant-current source through which the first and second transistors have their respective emitters commonly connected to the second supply voltage line, and a third transistor having its collector connected to the first voltage supply line, its base connected to the first voltage supply line through the load resistor and to the collector of the first transistor and its emitter connected to the base of the second transistor. There is further provided a second constant-current source through which the third transistor has its base further connected to the second voltage supply line.

Abstract: In a master-slave type flip-flop circuit, a plurality of bipolar type transistors are used for master and slave flip-flop circuits, and transistors are connected such that glitch noise can be prevented under all input conditions.