Patents by Inventor Yoshiteru Hayashi
Yoshiteru Hayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11941404Abstract: A processor performs, in accordance with a single instruction, multiplication processing and comparison processing. The multiplication processing includes obtaining a multiplication result by multiplying together a first data element and a first value. The comparison processing includes comparing the multiplication result with a second data element. The first data element is stored in a first register, the second data element is stored in a second register, and the first value is stored in a third register.Type: GrantFiled: July 14, 2021Date of Patent: March 26, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventor: Yoshiteru Hayashi
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Publication number: 20230305719Abstract: A data storage system is a data storage system which is mounted on a moving body. The data storage system includes: a plurality of ECUs which are connected to a network in the moving body; a shared storage device into which data is writable by each of the plurality of ECUs; and a shared priority controller which is connected between the plurality of ECUs and the shared storage device, and controls an order of priority in which data is written into the shared storage device from each of the plurality of ECUs.Type: ApplicationFiled: March 17, 2023Publication date: September 28, 2023Applicant: Panasonic Intellectual Property Management Co., Ltd.Inventors: Hiroki MONTA, Yoshiteru HAYASHI
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Publication number: 20220197972Abstract: An arithmetic processing system includes an external memory and an arithmetic-logic unit. The arithmetic-logic unit performs at least operations of 1) acquiring a first partition map from each input feature map stored in the external memory, the first partition map being one of partition maps included in the input feature map; executing a convolution operation on the first partition maps acquired from the external memory; storing, in the external memory, first partition maps that have undergone the convolution operation, and 2) acquiring a second partition map from each input feature map stored in the external memory, the second partition map being one of the partition maps; executing a convolution operation on the second partition maps acquired from the external memory; and storing, in the external memory, second partition maps that have undergone the convolution operation.Type: ApplicationFiled: March 10, 2022Publication date: June 23, 2022Applicant: Panasonic Intellectual Property Management Co., Ltd.Inventor: Yoshiteru HAYASHI
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Publication number: 20210342160Abstract: A processor performs, in accordance with a single instruction, multiplication processing and comparison processing. The multiplication processing includes obtaining a multiplication result by multiplying together a first data element and a first value. The comparison processing includes comparing the multiplication result with a second data element. The first data element is stored in a first register, the second data element is stored in a second register, and the first value is stored in a third register.Type: ApplicationFiled: July 14, 2021Publication date: November 4, 2021Applicant: Panasonic Intellectual Property Management Co., Ltd.Inventor: Yoshiteru HAYASHI
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Patent number: 10033997Abstract: An image decoding device is provided that decodes, without an increase in the circuit size, a coded video sequence including a large-size block. The image decoding apparatus includes: a block division unit which divides a current block that is to be decoded and is included in a picture of the coded video sequence, into sub-blocks; an image obtainment unit which obtains, for each of the sub-blocks, image data corresponding to the sub-block from a recording medium; a prediction unit which generates, for each of the sub-blocks, a predicted image of the sub-block, based on the image data obtained by the image obtainment unit; and a reconstruction unit which reconstructs each of the sub-blocks, by adding the predicted image generated for the sub-block to the sub-block.Type: GrantFiled: June 21, 2011Date of Patent: July 24, 2018Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yoshiteru Hayashi, Takeshi Tanaka, Takashi Hashimoto, Satoshi Kajita, Hiroshi Amano
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Patent number: 9641868Abstract: A moving image decoding apparatus which enables reduction in the memory bandwidth and the memory access latency for the motion compensation filter coefficients for use in inter-picture prediction involving motion compensation using variable coefficients includes: a decoding unit (101) which decodes, from a coded stream, a plurality of motion compensation filter coefficients; a memory (109) for holding the motion compensation filter coefficients included in the coded stream; a filter coefficient storage unit (103) for holding at least one of the motion compensation filter coefficients which is required for the motion compensation; a motion compensation unit (107) which performs motion compensation using the required motion compensation filter coefficient held in the filter coefficient storage unit; and a filter coefficient transfer control unit (102) which writes, in the memory, the motion compensation filter coefficients decoded by the decoding unit, and transfers the required motion compensation filter coeffType: GrantFiled: February 24, 2015Date of Patent: May 2, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hiroshi Amano, Takeshi Tanaka, Takashi Hashimoto, Yoshiteru Hayashi
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Publication number: 20150172723Abstract: A moving image decoding apparatus which enables reduction in the memory bandwidth and the memory access latency for the motion compensation filter coefficients for use in inter-picture prediction involving motion compensation using variable coefficients includes: a decoding unit (101) which decodes, from a coded stream, a plurality of motion compensation filter coefficients; a memory (109) for holding the motion compensation filter coefficients included in the coded stream; a filter coefficient storage unit (103) for holding at least one of the motion compensation filter coefficients which is required for the motion compensation; a motion compensation unit (107) which performs motion compensation using the required motion compensation filter coefficient held in the filter coefficient storage unit; and a filter coefficient transfer control unit (102) which writes, in the memory, the motion compensation filter coefficients decoded by the decoding unit, and transfers the required motion compensation filter coeffType: ApplicationFiled: February 24, 2015Publication date: June 18, 2015Inventors: Hiroshi AMANO, Takeshi TANAKA, Takashi HASHIMOTO, Yoshiteru HAYASHI
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Patent number: 9042457Abstract: An image decoding apparatus which decodes, in parallel, a coded stream having processing order dependency includes: a slice data predecoding unit which predecodes, on a macroblock group basis, macroblock groups included in the coded stream to generate macroblock decoding information necessary for decoding other macroblock groups; and a first macroblock decoding unit and a second macroblock decoding unit each of which decodes a corresponding one of macroblock groups included in the coded stream in parallel. Each of the macroblock decoding units, when decoding the corresponding one of macroblock groups, uses the macroblock decoding information that has been generated for the other macroblock group.Type: GrantFiled: June 5, 2009Date of Patent: May 26, 2015Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yoshiteru Hayashi, Hiroshi Amano, Masayasu Iguchi
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Patent number: 8995530Abstract: A moving image decoding apparatus which enables reduction in the memory bandwidth and the memory access latency for the motion compensation filter coefficients for use in inter-picture prediction involving motion compensation using variable coefficients includes: a decoding unit (101) which decodes, from a coded stream, a plurality of motion compensation filter coefficients; a memory (109) for holding the motion compensation filter coefficients included in the coded stream; a filter coefficient storage unit (103) for holding at least one of the motion compensation filter coefficients which is required for the motion compensation; a motion compensation unit (107) which performs motion compensation using the required motion compensation filter coefficient held in the filter coefficient storage unit; and a filter coefficient transfer control unit (102) which writes, in the memory, the motion compensation filter coefficients decoded by the decoding unit, and transfers the required motion compensation filter coeffType: GrantFiled: March 2, 2011Date of Patent: March 31, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Hiroshi Amano, Takeshi Tanaka, Takashi Hashimoto, Yoshiteru Hayashi
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Patent number: 8989512Abstract: A symmetric filter arithmetic apparatus includes a first data shuffling unit which reads a first data string that is a plurality of consecutive pieces of data from a register file and extract, from the first data string, a left-side data string that is a plurality of consecutive pieces of data to be multiplied by a left-side filter coefficient that is a filter coefficient on a left side of a center of the coefficients, and a second data shuffling unit which reads a second data string that is a plurality of consecutive pieces of data from the register file and extract, from the second data string, a right-side data string that is a plurality of consecutive pieces of data to be multiplied by a right-side filter coefficient that is a filter coefficient on a right side of the center and is the same value as the left-side filter coefficient.Type: GrantFiled: July 25, 2012Date of Patent: March 24, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventor: Yoshiteru Hayashi
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Patent number: 8897582Abstract: A decoding apparatus according to the present invention includes: a decoding unit which decodes identification information identifying an orthogonal transform basis for inverse orthogonal transform; an orthogonal transform basis accumulation unit accumulating orthogonal transform bases for inverse orthogonal transform; an orthogonal transform basis storage unit storing an orthogonal transform basis for inverse transform, from among the stored orthogonal transform bases; an inverse orthogonal transform unit which performs inverse orthogonal transform using the identified orthogonal transform basis; and an orthogonal transform basis transfer control unit which transfers the identified orthogonal transfer basis from the orthogonal transform basis accumulation unit to the orthogonal transfer basis storage unit only when the identified orthogonal transform basis is not yet stored therein.Type: GrantFiled: September 6, 2013Date of Patent: November 25, 2014Assignee: Panasonic CorporationInventors: Hiroshi Amano, Takeshi Tanaka, Takashi Hashimoto, Yoshiteru Hayashi
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Publication number: 20140219577Abstract: A symmetric filter arithmetic apparatus includes a first data shuffling unit which reads a first data string that is a plurality of consecutive pieces of data from a register file and extract, from the first data string, a left-side data string that is a plurality of consecutive pieces of data to be multiplied by a left-side filter coefficient that is a filter coefficient on a left side of a center of the coefficients, and a second data shuffling unit which reads a second data string that is a plurality of consecutive pieces of data from the register file and extract, from the second data string, a right-side data string that is a plurality of consecutive pieces of data to be multiplied by a right-side filter coefficient that is a filter coefficient on a right side of the center and is the same value as the left-side filter coefficient.Type: ApplicationFiled: July 25, 2012Publication date: August 7, 2014Inventor: Yoshiteru Hayashi
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Patent number: 8737476Abstract: An image decoding device capable of performing parallel decoding of coded image data with a small memory bandwidth while suppressing momentary increase in the amount of data transferred for the decoding. An image decoding device (100) includes: an external memory (110) which stores data of reference images; a stream parser unit (120) which decodes reference information indicating the number of reference images to be referred to on a block-by-block basis; an amount-of-transferred-data prediction unit (131) which calculates, on a block-by-block basis using the reference information, a predictive data amount of a reference image to be read out from the external memory (110); a block determination unit (132) which determines, using the predictive data amount, multiple blocks to be decoded in parallel, so as to reduce variation in amounts of data read out from the external memory (110); and macroblock decoding units (140 to 160) which decode the determined blocks in parallel.Type: GrantFiled: October 20, 2009Date of Patent: May 27, 2014Assignee: Panasonic CorporationInventor: Yoshiteru Hayashi
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Publication number: 20140010311Abstract: A decoding apparatus according to the present invention includes: a decoding unit which decodes identification information identifying an orthogonal transform basis for inverse orthogonal transform; an orthogonal transform basis accumulation unit accumulating orthogonal transform bases for inverse orthogonal transform; an orthogonal transform basis storage unit storing an orthogonal transform basis for inverse transform, from among the stored orthogonal transform bases; an inverse orthogonal transform unit which performs inverse orthogonal transform using the identified orthogonal transform basis; and an orthogonal transform basis transfer control unit which transfers the identified orthogonal transfer basis from the orthogonal transform basis accumulation unit to the orthogonal transfer basis storage unit only when the identified orthogonal transform basis is not yet stored therein.Type: ApplicationFiled: September 6, 2013Publication date: January 9, 2014Applicant: Panasonic CorporationInventors: Hiroshi AMANO, Takeshi TANAKA, Takashi HASHIMOTO, Yoshiteru HAYASHI
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Patent number: 8559736Abstract: A decoding apparatus (100) according to the present invention includes: a decoding unit (101) which decodes identification information identifying an orthogonal transform basis for inverse orthogonal transform; an orthogonal transform basis accumulation unit (110) accumulating orthogonal transform bases for inverse orthogonal transform; an orthogonal transform basis storage unit (103) storing an orthogonal transform basis for inverse transform, from among the stored orthogonal transform bases; an inverse orthogonal transform unit (112) which performs inverse orthogonal transform using the identified orthogonal transform basis; and an orthogonal transform basis transfer control unit (102) which transfers the identified orthogonal transfer basis from the orthogonal transform basis accumulation unit (110) to the orthogonal transfer basis storage unit (103) only when the identified orthogonal transform basis is not yet stored therein.Type: GrantFiled: March 16, 2011Date of Patent: October 15, 2013Assignee: Panasonic CorporationInventors: Hiroshi Amano, Takeshi Tanaka, Takashi Hashimoto, Yoshiteru Hayashi
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Publication number: 20130089149Abstract: An image decoding device is provided that decodes, without an increase in the circuit size, a coded video sequence including a large-size block. The image decoding apparatus includes: a block division unit which divides a current block that is to be decoded and is included in a picture of the coded video sequence, into sub-blocks; an image obtainment unit which obtains, for each of the sub-blocks, image data corresponding to the sub-block from a recording medium; a prediction unit which generates, for each of the sub-blocks, a predicted image of the sub-block, based on the image data obtained by the image obtainment unit; and a reconstruction unit which reconstructs each of the sub-blocks, by adding the predicted image generated for the sub-block to the sub-block.Type: ApplicationFiled: June 21, 2011Publication date: April 11, 2013Inventors: Yoshiteru Hayashi, Takeshi Tanaka, Takashi Hashimoto, Satoshi Kajita, Hiroshi Amano
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Publication number: 20120147959Abstract: A moving image decoding apparatus which enables reduction in the memory bandwidth and the memory access latency for the motion compensation filter coefficients for use in inter-picture prediction involving motion compensation using variable coefficients includes: a decoding unit (101) which decodes, from a coded stream, a plurality of motion compensation filter coefficients; a memory (109) for holding the motion compensation filter coefficients included in the coded stream; a filter coefficient storage unit (103) for holding at least one of the motion compensation filter coefficients which is required for the motion compensation; a motion compensation unit (107) which performs motion compensation using the required motion compensation filter coefficient held in the filter coefficient storage unit; and a filter coefficient transfer control unit (102) which writes, in the memory, the motion compensation filter coefficients decoded by the decoding unit, and transfers the required motion compensation filter coeffType: ApplicationFiled: March 2, 2011Publication date: June 14, 2012Inventors: Hiroshi Amano, Takeshi Tanaka, Takashi Hashimoto, Yoshiteru Hayashi
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Publication number: 20120063693Abstract: A decoding apparatus (100) according to the present invention includes: a decoding unit (101) which decodes identification information identifying an orthogonal transform basis for inverse orthogonal transform; an orthogonal transform basis accumulation unit (110) accumulating orthogonal transform bases for inverse orthogonal transform; an orthogonal transform basis storage unit (103) storing an orthogonal transform basis for inverse transform, from among the stored orthogonal transform bases; an inverse orthogonal transform unit (112) which performs inverse orthogonal transform using the identified orthogonal transform basis; and an orthogonal transform basis transfer control unit (102) which transfers the identified orthogonal transfer basis from the orthogonal transform basis accumulation unit (110) to the orthogonal transfer basis storage unit (103) only when the identified orthogonal transform basis is not yet stored therein.Type: ApplicationFiled: March 16, 2011Publication date: March 15, 2012Inventors: Hiroshi Amano, Takeshi Tanaka, Takashi Hashimoto, Yoshiteru Hayashi
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Publication number: 20110235716Abstract: A decoding apparatus (100) includes: a first memory unit (20) storing pixel data of a decoded reference image to be referred to in decoding; a second memory unit (30) having a storage capacity smaller than that of the first memory unit (20) and providing a data reading speed faster than that provided by the first memory unit (20); a search area transfer unit (40) transferring, from the first memory unit (20) to the second memory unit (30), pixel data in a search area that is a part of the reference image and required to calculate a motion vector for the block; a motion vector operating unit (50) calculating the motion vector by repeatedly (i) reading out, from the second memory unit (30), the pixel data and (ii) performing a predetermined operation on the pixel data; and a decoding unit (60) decoding the block using the calculated motion vector.Type: ApplicationFiled: October 7, 2010Publication date: September 29, 2011Inventors: Takeshi Tanaka, Hiroshi Amano, Yoshiteru Hayashi, Takashi Hashimoto, Satoshi Kajita
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Publication number: 20110200115Abstract: An image decoding apparatus (40) which decodes, in parallel, a coded stream (Str) having processing order dependency includes: a slice data predecoding unit (402) which predecodes, on a macroblock group basis, macroblock groups included in the coded stream (Str) to generate macroblock decoding information (1001) necessary for decoding other macroblock groups; and a first macroblock decoding unit (404) and a second macroblock decoding unit (405) each of which decodes a corresponding one of macroblock groups included in the coded stream (Str) in parallel. Each of the macroblock decoding units (404, 405), when decoding the corresponding one of macroblock groups, uses the macroblock decoding information (1001) that has been generated for the other macroblock group.Type: ApplicationFiled: June 5, 2009Publication date: August 18, 2011Inventors: Yoshiteru Hayashi, Hiroshi Amano, Masayasu Iguchi