Abstract: An image display is provided with a display area including pixels, each including illuminating means. A control circuit turns the illuminating means of the pixels on and off. A first terminal of a capacitor is connected to an input terminal of the control circuit. An image signal voltage generation circuit generates image signal voltages and a pixel drive voltage generation circuit generates pixel drive voltages for the pixels. A connector is provided for connecting either one of the image signal voltages or the pixel drive voltages to a second terminal of the capacitor. As such, an amount of drive current for the pixels is controlled in accordance with both the pixel drive voltage and the image signal voltage.

Abstract: An image display is provided with a display area including pixels, each including illuminating means. A control circuit turns the illuminating means of the pixels on and off. A first terminal of a capacitor is connected to an input terminal of the control circuit. An image signal voltage generation circuit generates image signal voltages and a pixel drive voltage generation circuit generates pixel drive voltages for the pixels. A connector is provided for connecting either one of the image signal voltages or the pixel drive voltages to a second terminal of the capacitor. As such, an amount of drive current for the pixels is controlled in accordance with both the pixel drive voltage and the image signal voltage.

Abstract: An image display is provided with a display area including pixels, each including illuminating means. A control circuit turns the illuminating means of the pixels on and off. A capacitance is provided having a first node connected to an input terminal of the control circuit. A display signal voltage generation circuit generates display signal voltages for the pixels, while a pixel drive voltage generation circuit generates pixel drive voltages for the pixels. In addition, a connector is provided for connecting either one of the display signal voltages or the pixel drive voltages to a second node of the capacitance.

Abstract: An image display is provided with a display area including pixels, each including illuminating means. A control circuit turns the illuminating means of the pixels on and off. A capacitance is provided having a first node connected to an input terminal of the control circuit. A display signal voltage generation circuit generates display signal voltages for the pixels, while a pixel drive voltage generation circuit generates pixel drive voltages for the pixels. In addition, a connecter is provided for connecting either one of the display signal voltages or the pixel drive voltages to a second node of the capacitance.

Abstract: An image display is provided with a display area including pixels, each including illuminating means. A control circuit turns the illuminating means of the pixels on and off. A capacitance is provided having a first node connected to an input terminal of the control circuit. A display signal voltage generation circuit generates display signal voltages for the pixels, while a pixel drive voltage generation circuit generates pixel drive voltages for the pixels. In addition, a connecter is provided for connecting either one of the display signal voltages or the pixel drive voltages to a second node of the capacitance.

Abstract: Disclosed is a simulation apparatus including an input unit, storage unit, arithmetic unit, controller, and output unit. The input unit inputs a first potential at the source end, which corresponds to the gate end of a TFT, on that surface of a thin polysilicon film which faces the gate, a second potential at the source end on the back surface of the thin polysilicon film on which the gate is formed, a third potential at the drain end, which corresponds to the gate end of the TFT, on that surface of the thin polysilicon film which faces the gate, and a fourth potential at the drain end on the back surface of the thin polysilicon film. A drain current is calculated by performing an arithmetic operation on the basis of the first to fourth potentials, and a model is formed by including defect states.

Abstract: Disclosed is a simulation apparatus including an input unit, storage unit, arithmetic unit, controller, and output unit. The input unit inputs a first potential at the source end, which corresponds to the gate end of a TFT, on that surface of a thin polysilicon film which faces the gate, a second potential at the source end on the back surface of the thin polysilicon film on which the gate is formed, a third potential at the drain end, which corresponds to the gate end of the TFT, on that surface of the thin polysilicon film which faces the gate, and a fourth potential at the drain end on the back surface of the thin polysilicon film. A drain current is calculated by performing an arithmetic operation on the basis of the first to fourth potentials, and a model is formed by including defect states.

Abstract: An image display is provided with a display area including pixels, each including illuminating means. A control circuit turns the illuminating means of the pixels on and off. A capacitance is provided having a first node connected to an input terminal of the control circuit. A display signal voltage generation circuit generates display signal voltages for the pixels, while a pixel drive voltage generation circuit generates pixel drive voltages for the pixels. In addition, a connecter is provided for connecting either one of the display signal voltages or the pixel drive voltages to a second node of the capacitance.

Abstract: An image display is provided with a display area including pixels, each including illuminating means. A control circuit turns the illuminating means of the pixels on and off. A capacitance is provided having a first node connected to an input terminal of the control circuit. A display signal voltage generation circuit generates display signal voltages for the pixels, while a pixel drive voltage generation circuit generates pixel drive voltages for the pixels. In addition, a connecter is provided for connecting either one of the display signal voltages or the pixel drive voltages to a second node of the capacitance.

Abstract: An image display capable of multilevel display and having a minimal pixel-to-pixel display characteristic variation. The image display having a display area of a plurality of pixels and a signal line for feeding a display signal voltage to the pixels, comprises, in at least one of the plurality of pixels: a memory for storing the display signal voltage entered from the signal line to the pixel; a pixel turn-on period decision section for determining an ON period and an OFF period for an image output in the pixel according to the display signal voltage; and a pixel driver for repeating an ON operation of the image output a plurality of times in one frame.

Abstract: An image display capable of multilevel display and having a minimal pixel-to-pixel display characteristic variation. The image display having a display area of a plurality of pixels and a signal line for feeding a display signal voltage to the pixels, comprises, in at least one of the plurality of pixels: a memory for storing the display signal voltage entered from the signal line to the pixel; a pixel turn-on period decision section for determining an ON period and an OFF period for an image output in the pixel according to the display signal voltage; and a pixel driver for repeating an ON operation of the image output a plurality of times in one frame.

Abstract: An image display is provided with a display area including pixels, each including illuminating means. A control circuit turns the illuminating means of the pixels on and off. A capacitance is provided having a first node connected to an input terminal of the control circuit. A display signal voltage generation circuit generates display signal voltages for the pixels, while a pixel drive voltage generation circuit generates pixel drive voltages for the pixels. In addition, a connecter is provided for connecting either one of the display signal voltages or the pixel drive voltages to a second node of the capacitance.

Abstract: An image display capable of multilevel display and having a minimal pixel-to-pixel display characteristic variation. The image display having a display area of a plurality of pixels and a signal line for feeding a display signal voltage to the pixels, comprises, in at least one of the plurality of pixels: a memory for storing the display signal voltage entered from the signal line to the pixel; a pixel turn-on period decision section for determining an ON period and an OFF period for an image output in the pixel according to the display signal voltage; and a pixel driver for repeating an ON operation of the image output a plurality of times in one frame.

Abstract: An image display capable of multilevel display and having a minimal pixel-to-pixel display characteristic variation. The image display having a display area of a plurality of pixels and a signal line for feeding a display signal voltage to the pixels, comprises, in at least one of the plurality of pixels: a memory for storing the display signal voltage entered from the signal line to the pixel; a pixel turn-on period decision section for determining an ON period and an OFF period for an image output in the pixel according to the display signal voltage; and a pixel driver for repeating an ON operation of the image output a plurality of times in one frame.

Abstract: A novel semiconductor device with a pair of main surfaces is disclosed, in which at least three semiconductor layers are formed adjacently to each other. The device comprises a main thyristor portion for supplying a main current, an auxiliary thyristor portion, a pilot thyristor portion and a breakover portion. The breakover portion, in turn, includes a semiconductor layer having a high impurities concentration formed on one of the main surfaces, and a plurality of semiconductor layers having a high impurities concentration of opposite conduction type formed adjacently to the semiconductor layer and in spaced relationship from each other.

Abstract: A semiconductor device has a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type contacted by respective first and second electrodes. A semi-insulating layer extends between the first and second electrodes and there is a first insulating layer between the semi-insulating layer and the first semiconductor region. The sheet resistivity of the semi-insulating layer varies, and this improves the high breakdown voltage of the p-n junction of the semiconductor device between the first and second semiconductor layers, by acting as a shield for charges included on a passivation insulation layer covering the semi-insulating layer and the first and second electrodes. Third semiconductor regions, with corresponding third electrodes, extend around, and are spaced from, the second semiconductor region.

Abstract: A semiconductor substrate of the shape of a disc possesses a first main surface and a second main surface. The semiconductor substrate consists of an emitter layer on the side of the cathode, a second base layer, a first base layer, and an emitter layer on the side of the anode, which are laminated in the order mentioned from the side of the cathode toward the side of the anode. The circumference of the emitter layer on the anode side is short-circuited by an emitter short-circuiting layer on the anode side. On the second main surface is arrayed the emitter layer on the cathode side being divided into a plurality of strip units which are oriented in a radial manner from the center toward the periphery of the semiconductor substrate. The second base layer is exposed on the other portions on the second main surface. The emitter layers on the anode side are provided in the portions where the emitter layers on the cathode side are projected onto the anode side.

Abstract: There is provided a light triggered thyristor device comprising a main thyristor triggered by an electric triggering signal, an auxiliary thyristor triggered by a light signal applied to a light receiving portion, the auxiliary thyristor then supplying the electric triggering signal from a cathode thereof to a gate of the main thyristor, a cylindrical insulator for containing the main thyristor, a connector mechanism disposed near an end of an anode on a side face of the main thyristor and electrically connected to the anode of the main thyristor, the connector mechanism having one end side exposed to outside of the cylindrical insulator, the auxiliary thyristor being so attached to one end side of the connector mechanism as to enable their free connection and disconnection, the anode of the main thyristor being electrically connected to the anode of the auxiliary thyristor via the connector mechanism.

Abstract: A main thyristor region is formed which comprises four continuous layers of alternately different conductivities consisting of first, second, third and fourth layers, PNPN for example. The main thyristor region constitutes a main thyristor section together with a couple of main electrodes in ohmic contact with the outside ones of the four layers. A pilot thyristor section and an auxiliary pilot thyristor section are constituted by employing the first, second and third layers of the main thyristor section and the main electrode in ohmic contact with the outside of the first layer and further by introducing fifth and sixth layers for forming PH junctions with the third layer. Further, there are provided a gate means for turning on the pilot thyristor section and an auxiliary gate means being in contact with the fifth or sixth layer.

Abstract: A semi-conductor device comprising a silicon body having an exposed surface of N-type conductivity layer and a substrate bonded to the exposed surface by means of a layer of a new solder material, the solder material being an alloy consisting essentially of 2 to 12% by weight of at least one element of Group V of the periodic table, preferably antimony, and 0.01 to 5% by weight of at least one of rare earth elements, for example, Misch metal and aluminum being balance on the basis of total weight of the solder material. An increase in FVD of the device in which a conventional aluminum solder is used is prevented by the use of the new solder materials.