Patents by Inventor Yoshito Fujii

Yoshito Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11460254
    Abstract: A heat pipe includes a container including a container substrate and a working fluid enclosed in the container. The working fluid contains water. The heat pipe includes a first film containing tin and/or a tin alloy on at least an inner surface of the container substrate and a second film formed on at least a part of a surface of the first film and containing an oxide and/or hydroxide containing tin.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: October 4, 2022
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Yoshito Fujii, Tomoaki Toratani
  • Publication number: 20200208922
    Abstract: Provided are a heat pipe capable of preventing the corrosion of a container and the generation of a hydrogen gas caused by a working fluid containing water even if the container is subjected to plastic deformation such as bending or an object to be cooled having a large amount of heat generation is thermally connected, and a method for manufacturing the heat pipe. The heat pipe includes a container including a container substrate and a working fluid enclosed in the container. The working fluid contains water. The heat pipe includes a first film containing tin and/or a tin alloy on at least an inner surface of the container substrate and a second film formed on at least a part of a surface of the first film and containing an oxide and/or hydroxide containing tin.
    Type: Application
    Filed: February 21, 2020
    Publication date: July 2, 2020
    Applicant: Furukawa Electric Co., Ltd.
    Inventors: Yoshito FUJII, Tomoaki TORATANI
  • Patent number: 10468283
    Abstract: A first conveyance mechanism and a second conveyance mechanism convey a pair of two wafers to an alignment device from a wafer container via a buffer device, and then bring the wafers respectively into a first load lock chamber and a second load lock chamber after alignment. An intermediate conveyance mechanism conveys one of the pair of two wafers between the first load lock chamber and a vacuum processing chamber. The intermediate conveyance mechanism conveys the other of the pair of two wafers between the second load lock chamber and the vacuum processing chamber. The first conveyance mechanism and the second conveyance mechanism take out the pair of two wafers subjected to an implantation process from the first load lock chamber and the second load lock chamber and store the wafers into the wafer container.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: November 5, 2019
    Assignee: SUMITOMO HEAVY INDUSTRIES ION TECHNOLOGY CO., LTD.
    Inventors: Tetsuya Kudo, Shinji Ebisu, Yoshito Fujii
  • Patent number: 9666413
    Abstract: Provided is an ion implantation apparatus including: a vacuum processing chamber in which an ion implantation process for a wafer is performed; one or more load lock chambers that are used for bringing the wafer into the vacuum processing chamber and taking out the wafer from the vacuum processing chamber; an intermediate conveyance chamber that is disposed to be adjacent to both the vacuum processing chamber and the load lock chamber; a load lock chamber-intermediate conveyance chamber communication mechanism including a gate valve capable of sealing a load lock chamber-intermediate conveyance chamber communication port; and an intermediate conveyance chamber-vacuum processing chamber communication mechanism including a movable shielding plate capable of shielding a part or the whole of the intermediate conveyance chamber-vacuum processing chamber communication port.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: May 30, 2017
    Assignee: SUMITOMO HEAVY INDUSTRIES ION TECHNOLOGY CO., LTD.
    Inventors: Yoshito Fujii, Tetsuya Kudo, Shinji Ebisu, Suguru Hirokawa, Keiji Okada
  • Publication number: 20170040197
    Abstract: A first conveyance mechanism and a second conveyance mechanism convey a pair of two wafers to an alignment device from a wafer container via a buffer device, and then bring the wafers respectively into a first load lock chamber and a second load lock chamber after alignment. An intermediate conveyance mechanism conveys one of the pair of two wafers between the first load lock chamber and a vacuum processing chamber. The intermediate conveyance mechanism conveys the other of the pair of two wafers between the second load lock chamber and the vacuum processing chamber. The first conveyance mechanism and the second conveyance mechanism take out the pair of two wafers subjected to an implantation process from the first load lock chamber and the second load lock chamber and store the wafers into the wafer container.
    Type: Application
    Filed: August 4, 2016
    Publication date: February 9, 2017
    Inventors: Tetsuya Kudo, Shinji Ebisu, Yoshito Fujii
  • Publication number: 20160009880
    Abstract: A novel film material that is capable of reducing an amount of carbon dioxide discharged during incineration for disposal is provided. The novel film material is a stretch film formed to a thickness in a range of 5 to 50 ?m. The stretch film contains a thermoplastic resin composition that includes a carbon dioxide absorbing substance in an amount in a range of 0.1 to 10 wt %.
    Type: Application
    Filed: June 29, 2015
    Publication date: January 14, 2016
    Inventors: Masahiko ABE, Masamitsu NAGAHAMA, Shigeru KIDO, Akira SATO, Masatoshi TAKAHASHI, Yoshito FUJII, Hiromi YAMAMURO, Yoshihisa YAMAUCHI
  • Publication number: 20150364299
    Abstract: Provided is an ion implantation apparatus including: a vacuum processing chamber in which an ion implantation process for a wafer is performed; one or more load lock chambers that are used for bringing the wafer into the vacuum processing chamber and taking out the wafer from the vacuum processing chamber; an intermediate conveyance chamber that is disposed to be adjacent to both the vacuum processing chamber and the load lock chamber; a load lock chamber-intermediate conveyance chamber communication mechanism including a gate valve capable of sealing a load lock chamber-intermediate conveyance chamber communication port; and an intermediate conveyance chamber-vacuum processing chamber communication mechanism including a movable shielding plate capable of shielding a part or the whole of the intermediate conveyance chamber-vacuum processing chamber communication port.
    Type: Application
    Filed: June 16, 2015
    Publication date: December 17, 2015
    Inventors: Yoshito Fujii, Tetsuya Kudo, Shinji Ebisu, Suguru Hirokawa, Keiji Okada
  • Patent number: 8709939
    Abstract: A multilevel interconnect structure in a semiconductor device and methods for fabricating the same are described. The multilevel interconnect structure in the semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: April 29, 2014
    Assignees: Semiconductor Technology Academic Research Center, National University Corporation Tohoku University
    Inventors: Junichi Koike, Yoshito Fujii, Jun Iijima, Noriyoshi Shimizu, Kazuyoshi Maekawa, Koji Arita, Ryotaro Yagi, Masaki Yoshimaru
  • Patent number: 8304908
    Abstract: A multilevel interconnect structure in a semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: November 6, 2012
    Assignees: Semiconductor Technology Academic Research Center, National University Corporation Tohoku University
    Inventors: Junichi Koike, Yoshito Fujii, Jun Iijima, Noriyoshi Shimizu, Kazuyoshi Maekawa, Koji Arita, Ryotaro Yagi, Masaki Yoshimaru
  • Patent number: D656472
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: March 27, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Katsuhiro Iida, Tohru Ohtani, Yoshito Fujii, Takeshi Kodera, Hiroshi Yamamizu, Kohichi Iida
  • Patent number: D657327
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: April 10, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Katsuhiro Iida, Tohru Ohtani, Yoshito Fujii, Takeshi Kodera, Hiroshi Yamamizu, Kohichi Iida
  • Patent number: D669523
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: October 23, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kuniharu Wakata, Yasuhiko Oda, Keiichiro Aou, Yoshito Fujii
  • Patent number: D678230
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: March 19, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Yamamizu, Masaki Iinuma, Yoshito Fujii
  • Patent number: D679671
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: April 9, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshito Fujii, Hiroshi Gomi, Keiichiro Aou
  • Patent number: D679672
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: April 9, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshito Fujii, Hiroshi Gomi, Keiichiro Aou
  • Patent number: D680087
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: April 16, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshito Fujii, Katsuhiro Iida, Tohru Ohtani, Hiroshi Gomi
  • Patent number: D687000
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: July 30, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Gomi, Keiichiro Aou, Yoshito Fujii
  • Patent number: D694210
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: November 26, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshito Fujii, Noriaki Itai, Hiroshi Yamamizu, Hiroshi Gomi, Kuniharu Wakata, Masaki Iinuma
  • Patent number: D711453
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: August 19, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshito Fujii, Harumi Sakamoto, Kunihara Wakata, Keiichi Takao
  • Patent number: D711454
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: August 19, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshito Fujii, Harumi Sakamoto, Kunihara Wakata, Keiichi Takao