Patents by Inventor Yoshito Katano
Yoshito Katano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8601191Abstract: Disclosed herein is a deadlock avoidance circuit including: a previous-transaction-information management section; a transaction-issuance-termination determination section; and a response-outputting control section.Type: GrantFiled: July 27, 2011Date of Patent: December 3, 2013Assignee: Sony CorporationInventors: Sumie Aoki, Yoshito Katano
-
Patent number: 8200882Abstract: A memory system includes: a memory that has plural banks; a memory controller that includes a request queue and a bank monitor and controls access to the memory; a master group including plural masters that can request access to the memory; and a system bus which is connected between the memory controller and the master group and in which an arbiter is arranged, wherein the request queue has a scheduling function for receiving access requests issued from the master group through the system bus and appropriately rearranging the received access requests and provides the arbiter with queue information, the bank monitor monitors information concerning respective banks of the memory and provides the arbiter with the bank information, and the arbiter arbitrates requests issued in parallel from the masters of the master group on the basis of the queue information and the bank information provided thereto and transmits the information to the memory controller as access control information.Type: GrantFiled: June 16, 2009Date of Patent: June 12, 2012Assignee: Sony CorporationInventors: Hideo Tanaka, Yoshito Katano
-
Publication number: 20120079150Abstract: Disclosed herein is a deadlock avoidance circuit including: a previous-transaction-information management section; a transaction-issuance-termination determination section; and a response-outputting control section.Type: ApplicationFiled: July 27, 2011Publication date: March 29, 2012Applicant: Sony CorporationInventors: Sumie Aoki, Yoshito Katano
-
Patent number: 8135991Abstract: A flash memory is made to store a same boot program in a plurality of blocks in it. When a flash memory controller receives an access command for accessing the storage region storing the boot program from a CPU (Step S101), it outputs the read out data to the CPU only when the corresponding block is not faulty according to the determination (Steps S105, S106) made on the basis of the ECC contained in the data read out from the corresponding page and the determination (Step S109) made on the basis of the block information also contained in the data read out from the corresponding page. If, on the other hand it is determined that the block is faulty, the flash memory controller reads out the boot program stored in the next block (Steps S106, S103) and determines once again that the block is faulty or not faulty.Type: GrantFiled: January 27, 2005Date of Patent: March 13, 2012Assignee: Sony CorporationInventors: Yoshito Katano, Tadashi Yoshida, Kazuhiro Sako
-
Publication number: 20090319730Abstract: A memory system includes: a memory that has plural banks; a memory controller that includes a request queue and a bank monitor and controls access to the memory; a master group including plural masters that can request access to the memory; and a system bus which is connected between the memory controller and the master group and in which an arbiter is arranged, wherein the request queue has a scheduling function for receiving access requests issued from the master group through the system bus and appropriately rearranging the received access requests and provides the arbiter with queue information, the bank monitor monitors information concerning respective banks of the memory and provides the arbiter with the bank information, and the arbiter arbitrates requests issued in parallel from the masters of the master group on the basis of the queue information and the bank information provided thereto and transmits the information to the memory controller as access control information.Type: ApplicationFiled: June 16, 2009Publication date: December 24, 2009Applicant: Sony CorporationInventors: Hideo Tanaka, Yoshito Katano
-
Publication number: 20080046637Abstract: A flash memory is made to store a same boot program in a plurality of blocks in it. When a flash memory controller receives an access command for accessing the storage region storing the boot program from a CPU (Step S101), it outputs the read out data to the CPU only when the corresponding block is not faulty according to the determination (Steps S105, S106) made on the basis of the ECC contained in the data read out from the corresponding page and the determination (Step S109) made on the basis of the block information also contained in the data read out from the corresponding page. If, on the other hand it is determined that the block is faulty, the flash memory controller reads out the boot program stored in the next block (Steps S106, S103) and determines once again that the block is faulty or not faulty.Type: ApplicationFiled: January 27, 2005Publication date: February 21, 2008Inventors: Yoshito Katano, Tadashi Yoshida, Kazuhiro Sako
-
Patent number: 6748406Abstract: When one clock signal (CLK) is output, the following operations are performed: an input data signal D is latched by a data latch; a detection-type signal K is latched by a signal latch; the input data signal D is input to a 1 detecting circuit and a 0 detecting circuit, which are connected in parallel, while the data latch holds the input data signal D; for example, a 1 detection process for detecting that bit data changes from 0 to 1 or a 0 detection process for detecting that bit data changes from 1 to 0 is performed; and either a 1 detection or a 0 detection output operation, which is selected by a selector circuit 27, is performed. As a result, a bit search process is quickly performed.Type: GrantFiled: June 26, 2002Date of Patent: June 8, 2004Assignee: Fujitsu LimitedInventor: Yoshito Katano
-
Patent number: 6560622Abstract: When one clock signal (CLK) is output, the following operations are performed: an input data signal D is latched by a data latch; a detection-type signal K is latched by a signal latch; the input data signal D is input to a 1 detecting circuit and a 0 detecting circuit, which are connected in parallel, while the data latch holds the input data signal D; for example, a 1 detection process for detecting that bit data changes from 0 to 1 or a 0 detection process for detecting that bit data changes from 1 to 0 is performed; and either a 1 detection or a 0 detection output operation, which is selected by a selector circuit 27, is performed. As a result, a bit search process is quickly performed.Type: GrantFiled: May 26, 1999Date of Patent: May 6, 2003Assignee: Fujitsu LimitedInventor: Yoshito Katano
-
Publication number: 20020194233Abstract: When one clock signal (CLK) is output, the following operations are performed: an input data signal D is latched by a data latch; a detection-type signal K is latched by a signal latch; the input data signal D is input to a 1 detecting circuit and a 0 detecting circuit, which are connected in parallel, while the data latch holds the input data signal D; for example, a 1 detection process for detecting that bit data changes from 0 to 1 or a 0 detection process for detecting that bit data changes from 1 to 0 is performed; and either a 1 detection or a 0 detection output operation, which is selected by a selector circuit 27, is performed. As a result, a bit search process is quickly performed.Type: ApplicationFiled: May 26, 1999Publication date: December 19, 2002Inventor: YOSHITO KATANO
-
Publication number: 20020169809Abstract: When one clock signal (CLK) is output, the following operations are performed: an input data signal D is latched by a data latch; a detection-type signal K is latched by a signal latch; the input data signal D is input to a 1 detecting circuit and a 0 detecting circuit, which are connected in parallel, while the data latch holds the input data signal D; for example, a 1 detection process for detecting that bit data changes from 0 to 1 or a 0 detection process for detecting that bit data changes from 1 to 0 is performed; and either a 1 detection or a 0 detection output operation, which is selected by a selector circuit 27, is performed. As a result, a bit search process is quickly performed.Type: ApplicationFiled: June 26, 2002Publication date: November 14, 2002Applicant: Fujitsu LimitedInventor: Yoshito Katano