Patents by Inventor Yoshitomo Fujisawa

Yoshitomo Fujisawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10980160
    Abstract: An image pickup module includes a printed wiring board, an electronic component, solder, and a thermosetting resin. The printed wiring board has a first surface provided with first lands. The electronic component includes an image pickup element and has a second surface provided with second lands. The thermosetting resin is in contact with the solder and bonds the printed wiring board to the electronic component. The solder bonds the first lands to the second lands and has a hollow portion. The area of the hollow portion is 5% to 50% of the total area of the solder as observed from the electronic component side in a transmission mode using an X-ray.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: April 13, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Mitsutoshi Hasegawa, Kunihiko Minegishi, Takashi Sakaki, Yoshitomo Fujisawa, Shingo Ishiguri
  • Publication number: 20200100408
    Abstract: An image pickup module includes a printed wiring board, an electronic component, solder, and a thermosetting resin. The printed wiring board has a first surface provided with first lands. The electronic component includes an image pickup element and has a second surface provided with second lands. The thermosetting resin is in contact with the solder and bonds the printed wiring board to the electronic component. The solder bonds the first lands to the second lands and has a hollow portion. The area of the hollow portion is 5% to 50% of the total area of the solder as observed from the electronic component side in a transmission mode using an X-ray.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 26, 2020
    Inventors: Mitsutoshi Hasegawa, Kunihiko Minegishi, Takashi Sakaki, Yoshitomo Fujisawa, Shingo Ishiguri
  • Patent number: 9111791
    Abstract: The printed circuit board (100) includes the interposer (2) where the semiconductor element (1) is mounted and the electrode pad (8) is formed on one surface, the printed wiring board (3) where the electrode pad (9) is formed on one surface facing the interposer (2), and the joint material (70) for bonding the electrode pads (8) and (9). The joint material (70) includes the solder layer (60) formed by the solder material (11) and the metal layers (50), (50) provided to the electrode pads (8) and (9). Each metal layer (50) includes the metal particle aggregate (10) in which metal particles are integrated with voids and is formed by filling the voids in the metal particle aggregate (10) with melted solder material (11). It is possible to ensure the height of the solder, improve reliability of the bonding, and downsize the semiconductor device by using such joint material.
    Type: Grant
    Filed: October 3, 2012
    Date of Patent: August 18, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yoshitomo Fujisawa
  • Patent number: 8853866
    Abstract: In a semiconductor device according to the present invention, a solder resist has a plurality of openings that expose electrodes. Solder bumps are formed in the openings and each have a solder ball portion protruding from the corresponding opening. The height of the openings is set to increase with increasing gap distance between the electrodes of an interposer substrate and board electrodes of a printed wiring board on which the semiconductor device is mounted. Thus, the solder bumps that correspond to sections where the gap distance is large can be increased in height, whereas the solder bumps that correspond to sections where the gap distance is small can be decreased in height, thereby avoiding the occurrence of defective joints caused by a reduction in size and thickness of the interposer substrate, as well as extending the lifespan of solder joints.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: October 7, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yoshitomo Fujisawa
  • Publication number: 20140231996
    Abstract: The printed circuit board (100) includes the interposer (2) where the semiconductor element (1) is mounted and the electrode pad (8) is formed on one surface, the printed wiring board (3) where the electrode pad (9) is formed on one surface facing the interposer (2), and the joint material (70) for bonding the electrode pads (8) and (9). The joint material (70) includes the solder layer (60) formed by the solder material (11) and the metal layers (50), (50) provided to the electrode pads (8) and (9). Each metal layer (50) includes the metal particle aggregate (10) in which metal particles are integrated with voids and is formed by filling the voids in the metal particle aggregate (10) with melted solder material (11). It is possible to ensure the height of the solder, improve reliability of the bonding, and downsize the semiconductor device by using such joint material.
    Type: Application
    Filed: October 3, 2012
    Publication date: August 21, 2014
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Yoshitomo Fujisawa
  • Publication number: 20120299183
    Abstract: In a semiconductor device according to the present invention, a solder resist has a plurality of openings that expose electrodes. Solder bumps are formed in the openings and each have a solder ball portion protruding from the corresponding opening. The height of the openings is set to increase with increasing gap distance between the electrodes of an interposer substrate and board electrodes of a printed wiring board on which the semiconductor device is mounted. Thus, the solder bumps that correspond to sections where the gap distance is large can be increased in height, whereas the solder bumps that correspond to sections where the gap distance is small can be decreased in height, thereby avoiding the occurrence of defective joints caused by a reduction in size and thickness of the interposer substrate, as well as extending the lifespan of solder joints.
    Type: Application
    Filed: February 10, 2011
    Publication date: November 29, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Yoshitomo Fujisawa