Abstract: A packet processing device which can reserve a calculation time for each instruction procedure execution unit independent of the data length of a packet by sequentially selecting an instruction procedure execution unit by a selection signal generation unit and performing a calculation on each packet when packets are consecutively input to a packet access unit is disclosed.

Abstract: A packet processor having a general-purpose arithmetic operator and another dedicated circuit, which extracts a particular field from the general-purpose register as object field, on which the predetermined general-purpose arithmetic operation is to be performed by the general-purpose arithmetic operator and writes a result of the arithmetic operation by the general-purpose arithmetic operator into the general-purpose register as updated information of the particular field. Based on the extraction and write process of the packet field designated by software (instructions), the packet processor realizes high flexibility and high speed processing.

Abstract: A packet-data-processing apparatus includes a first data-processing unit for computing information on a processing count; a memory; a second data-processing-unit for processing the input packet and storing first results in the memory; an access mechanism unit for reading out one of the first results written into the memory least recently from the memory at a request for a read operation and deleting the result of processing read out from the memory; a third data-processing unit for making the request for a read operation and carrying out processing based on the first result read out by the access control unit at the request and an input packet associated with the result of processing; and fourth data-processing unit constituting pipeline data-processing mechanism with the first and third data-processing unit.

Abstract: A packet-data-processing apparatus includes a first data-processing unit for computing information on a processing count; a memory; a second data-processing-unit for processing the input packet and storing first results in the memory; an access mechanism unit for reading out one of the first results written into the memory least recently from the memory at a request for a read operation and deleting the result of processing read out from the memory; a third data-processing unit for making the request for a read operation and carrying out processing based on the first result read out by the access control unit at the request and an input packet associated with the result of processing; and fourth data-processing unit constituting pipeline data-processing mechanism with said first and third data-processing unit.

Abstract: The packet processing device which can reserve a calculation time for each instruction procedure execution unit independent of the data length of a packet by sequentially selecting an instruction procedure execution unit by a selection signal generation unit and performing a calculation on each packet when packets are consecutively input to a packet access unit is disclosed.

Abstract: A packet processor having a general-purpose arithmetic operator and another dedicated circuit, which extracts a particular field from the general-purpose register as object field, on which the predetermined general-purpose arithmetic operation is to be performed by the general-purpose arithmetic operator and writes a result of the arithmetic operation by the general-purpose arithmetic operator into the general-purpose register as updated information of the particular field. Based on the extraction and write process of the packet field designated by software (instructions), the packet processor realizes high flexibility and high speed processing.