Abstract: A one-dimensional discrete cosine transform processor of N (N: positive integer)-term input data X includes a preprocessing section for carrying out addition and subtraction of (i)th-term data x (i) and (N-i)th-term data x (N-1) of input data X, and a unit for performing a product sum operation for sets of intermediate data subjected to preprocessing by addition and sets of intermediate data subjected to preprocessing by subtraction, respectively. The product sum operation unit includes a data rearranging unit for outputting, in parallel and in order, bit data of the same figure of a set of data, a partial sum generator for generating a partial sum by using the parallel bit data as an address, and an accumulator for accumulating outputs of the partial sum generator.

Abstract: The semiconductor integrated circuit device includes a select gate for selectively transmitting a signal. The select gate includes a first gate for receiving and transferring a first logic signal to an output node, and a second gate for receiving and transferring a second logic signal to the output node. The first and second gates turn on complementarily to each other. The first gate has an output load capacitance viewed from the output node less than that of the second gate. The first gate receives, as the first logic signal, a signal not required to be transmitted at a high speed, or a signal of a predetermined logic level or a fixed level. The second gate receives, as the second signal, a signal to be transmitted at a high speed. Since the second gate has a less output load capacitance, the second gate is allowed to transmit a signal at a high speed.

Abstract: A bus circuit comprises a bus interconnection (1) and a plurality of local bus interconnections (10). A plurality of circuit blocks (21a to 21d) are connected to each of the plurality of local bus interconnections (10). A multiplexer (70), a bus driver (60) and a transmitting circuit (80A) are provided corresponding to each of the local bus interconnections (10). Each multiplexer (70) selects one of the outputs from the corresponding plurality of circuit blocks (21a to 21d) and applies the selected one to the bus driver (60). The bus driver (60) drives the bus interconnection (1) according to the output of the multiplexer (70). The local bus interconnections (10) are precharged to a predetermined potential in advance. When any of the plurality of transmitting circuits (80A) is selected, the selected transmitting circuit (80A) either discharges the corresponding local bus interconnection (10) or holds the same at a predetermined potential according to the information on the bus interconnection (1).