Patents by Inventor Yoshiyuki Harumoto
Yoshiyuki Harumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220352118Abstract: A micro-LED mounting substrate includes a wiring line substrate provided with at least a plurality of substrate-side connecting portions on one plate surface, a plurality of micro-LEDs disposed side by side in the one plate surface of the wiring line substrate and each including at least a light-emitting face and an LED-side connecting portion provided on a surface opposite to the light-emitting face and connected to the substrate-side connecting portion, a first positioning portion provided on at least a portion of the plurality of micro-LEDs, and facing an installation surface of the substrate-side connecting portion of the wiring line substrate, and a second positioning portion provided on the installation surface of the substrate-side connecting portion of the wiring line substrate and capable of positioning the micro-LEDs including the first positioning portion by being recess-projection-fitted to the first positioning portion.Type: ApplicationFiled: April 18, 2022Publication date: November 3, 2022Inventors: Yoshiyuki HARUMOTO, YOSHITO HASHIMOTO
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Patent number: 9177974Abstract: An active matrix substrate includes a plurality of pixels arranged in a matrix, a plurality of capacitor lines (11b) extending in one of directions in which the pixels are aligned and in parallel to each other, a plurality of TFTs (5), one for each of the pixels, a protective film (16a) covering the TFTs (5), a plurality of pixel electrodes (18a) arranged in a matrix on the protective film (16a) and connected to the respective corresponding TFTs (5), and a plurality of auxiliary capacitors (6), one for each of the pixels. Each of the auxiliary capacitors (6) includes the corresponding capacitor line (11b), the corresponding pixel electrode (18a), and the protective film (16a) between the corresponding capacitor line (11b) and the corresponding pixel electrode (18a).Type: GrantFiled: July 26, 2010Date of Patent: November 3, 2015Assignee: Sharp Kabushiki KaishaInventors: Yoshimasa Chikama, Hirohiko Nishiki, Yoshifumi Ohta, Hinae Mizuno, Takeshi Hara, Tetsuya Aita, Masahiko Suzuki, Michiko Takei, Okifumi Nakagawa, Yoshiyuki Harumoto
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Patent number: 9142573Abstract: Each of the auxiliary capacitors (6a) includes a capacitor line (11b) comprised of the same material as the gate electrode (11a) and provided in the same layer as the gate electrode (11a), the gate insulating film (12) provided so as to cover the capacitor line (11a), a capacitor intermediate layer (13c) provided using the oxide semiconductor and provided on the gate insulating film (12) so as to overlap the capacitor line (11b), and a capacitor electrode (15b) provided on the capacitor intermediate layer (13c), and the capacitor intermediate layer (13c) is conductive.Type: GrantFiled: February 14, 2011Date of Patent: September 22, 2015Assignee: Sharp Kabushiki KaishaInventors: Tetsuya Yamashita, Tokuo Yoshida, Yoshimasa Chikama, Yoshifumi Ohta, Yuuji Mizuno, Hinae Mizuno, Masahiko Suzuki, Okifumi Nakagawa, Yoshiyuki Harumoto, Yoshinobu Miyamoto
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Patent number: 9076718Abstract: The present invention provides an oxide semiconductor capable of achieving a thin film transistor having stable transistor characteristics, a thin film transistor having a channel layer formed of the oxide semiconductor and a production method thereof, and a display device equipped with the thin film transistor. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor. The oxide semiconductor includes indium, gallium, zinc, and oxygen as constituent atoms, and the oxygen content of the oxide semiconductor is 87% to 95% of the stoichiometric condition set as 100%, in terms of atomic units.Type: GrantFiled: September 5, 2014Date of Patent: July 7, 2015Assignee: Sharp Kabushiki KaishaInventors: Yoshifumi Ohta, Go Mori, Hirohiko Nishiki, Yoshimasa Chikama, Tetsuya Aita, Masahiko Suzuki, Okifumi Nakagawa, Michiko Takei, Yoshiyuki Harumoto, Takeshi Hara
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Patent number: 9035295Abstract: A semiconductor device (100A) according to the present invention includes an oxide semiconductor layer (31a), first and second source electrodes (52a1 and 52a2), and first and second drain electrodes (53a1 and 53a2). The second source electrode (52a2) is formed to be in contact with a top surface of the first source electrode and inner to the first source electrode (52a1). The second drain electrode (53a2) is formed to be in contact with a top surface of the first drain electrode (53a1) and inner to the first drain electrode (53a1). The oxide semiconductor layer (31a) is formed to be in contact with the top surface of the first source electrode (52a1) and the top surface of the first drain electrode (53a1).Type: GrantFiled: April 5, 2011Date of Patent: May 19, 2015Assignee: Sharp Kabushiki KaishaInventors: Okifumi Nakagawa, Yoshifumi Ohta, Yoshimasa Chikama, Tsuyoshi Inoue, Masahiko Suzuki, Michiko Takei, Yoshiyuki Harumoto, Yoshinobu Miyamoto, Hinae Mizuno
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Patent number: 9024311Abstract: The present invention provides a thin film transistor including an oxide semiconductor layer (4) for electrically connecting a signal electrode (6a) and a drain electrode (7a), the an oxide semiconductor layer being made from an oxide semiconductor; and a barrier layer (6b) made from at least one selected from the group consisting of Ti, Mo, W, Nb, Ta, Cr, nitrides thereof, and alloys thereof, the barrier layer (6b) being in touch with the signal electrode (6a) and the oxide semiconductor layer (4) and separating the signal electrode (6a) from the oxide semiconductor layer (4). Because of this configuration, the thin film transistor can form and maintain an ohmic contact between the first electrode and the channel layer, thereby being a thin film transistor with good properties.Type: GrantFiled: April 6, 2010Date of Patent: May 5, 2015Assignee: Sharp Kabushiki KaishaInventors: Takeshi Hara, Hirohiko Nishiki, Yoshimasa Chikama, Kazuo Nakagawa, Yoshifumi Ohta, Tetsuya Aita, Masahiko Suzuki, Okifumi Nakagawa, Yoshiyuki Miyajima, Michiko Takei, Yoshiyuki Harumoto, Hinae Mizuno
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Publication number: 20140367683Abstract: The present invention provides an oxide semiconductor capable of achieving a thin film transistor having stable transistor characteristics, a thin film transistor having a channel layer formed of the oxide semiconductor and a production method thereof, and a display device equipped with the thin film transistor. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor. The oxide semiconductor includes indium, gallium, zinc, and oxygen as constituent atoms, and the oxygen content of the oxide semiconductor is 87% to 95% of the stoichiometric condition set as 100%, in terms of atomic units.Type: ApplicationFiled: September 5, 2014Publication date: December 18, 2014Inventors: Yoshifumi OHTA, Go MORI, Hirohiko NISHIKI, Yoshimasa CHIKAMA, Tetsuya AITA, Masahiko SUZUKI, Okifumi NAKAGAWA, Michiko TAKEI, Yoshiyuki HARUMOTO, Takeshi HARA
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Patent number: 8906739Abstract: A method includes: a step of forming a gate electrode (14) on a substrate (10a); a step of forming a gate insulating film (15) to cover the gate electrode (14), and then forming an In-Ga-Zn-O-based oxide semiconductor layer (16) in which a ratio of In:Ga:Zn in atomic % is 1:1:1 or 4:5:1 on the gate insulating film (15) to overlap the gate electrode (14); a step of forming a source electrode (19a) and a drain electrode (19b) on the oxide semiconductor layer (16) to overlap the gate electrode (14) and to face each other; and a step of performing an annealing process in an atmosphere containing steam (S) on the substrate (10a) provided with the source electrode (19a) and the drain electrode (19b).Type: GrantFiled: February 9, 2011Date of Patent: December 9, 2014Assignee: Sharp Kabushiki KaishaInventors: Yoshifumi Ohta, Yoshimasa Chikama, Masahiko Suzuki, Okifumi Nakagawa, Yoshiyuki Harumoto
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Patent number: 8865516Abstract: The present invention provides an oxide semiconductor capable of achieving a thin film transistor having stable transistor characteristics, a thin film transistor having a channel layer formed of the oxide semiconductor and a production method thereof, and a display device equipped with the thin film transistor. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor. The oxide semiconductor includes indium, gallium, zinc, and oxygen as constituent atoms, and the oxygen content of the oxide semiconductor is 87% to 95% of the stoichiometric condition set as 100%, in terms of atomic units.Type: GrantFiled: March 10, 2010Date of Patent: October 21, 2014Assignee: Sharp Kabushiki KaishaInventors: Yoshifumi Ohta, Go Mori, Hirohiko Nishiki, Yoshimasa Chikama, Tetsuya Aita, Masahiko Suzuki, Okifumi Nakagawa, Michiko Takei, Yoshiyuki Harumoto, Takeshi Hara
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Patent number: 8829513Abstract: The present invention provides an oxide semiconductor that realizes a TFT excellent in electric properties and process resistance, a TFT comprising a channel layer formed of the oxide semiconductor, and a display device equipped with the TFT. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor, wherein the oxide semiconductor contains Ga (gallium), In (indium), Zn (zinc), and O (oxygen) as constituent atoms, and the oxide semiconductor has Zn atomic composition satisfying the equation of 0.01?Zn/(In+Zn)?0.22.Type: GrantFiled: March 29, 2010Date of Patent: September 9, 2014Assignee: Sharp Kabushiki KaishaInventors: Yoshifumi Ota, Hirohiko Nishiki, Yoshimasa Chikama, Takeshi Hara, Tetsuya Aita, Masahiko Suzuki, Okifumi Nakagawa, Kazuo Nakagawa, Michiko Takei, Yoshiyuki Harumoto, Hinae Mizuno
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Patent number: 8823002Abstract: An object of this invention is to provide a semiconductor device in which TFTs with high mobility are arranged in both of display and peripheral circuit areas. A semiconductor device fabricating method according to the present invention includes the steps of: irradiating an amorphous silicon layer (34) with energy, thereby obtaining a microcrystalline silicon layer; and forming a doped semiconductor layer (35) on the amorphous silicon layer (34). In the step of irradiating, the amorphous silicon layer (34) is irradiated with energy that has a first quantity, thereby forming a first microcrystalline silicon layer (34A) including a channel layer for a first TFT (30A), and is also irradiated with energy that has a second quantity, which is larger than the first quantity, thereby forming a second microcrystalline silicon layer (34B) including a channel layer for a second TFT (30B).Type: GrantFiled: August 23, 2010Date of Patent: September 2, 2014Assignee: Sharp Kabushiki KaishaInventors: Michiko Takei, Tohru Okabe, Tetsuya Aita, Tsuyoshi Inoue, Yoshiyuki Harumoto, Takeshi Yaneda
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Patent number: 8698152Abstract: A display panel (50a) includes a TFT substrate (20a) in which a plurality of TFTs (5a) are provided, a counter substrate (30a) provided to face the TFT substrate (20a), and a display medium layer (40) provided between the TFT substrate (20a) and the counter substrate (30a), a plurality of pixels being provided so that each of the plurality of pixels is associated with a corresponding one of the TFTs (5a), wherein an oxide semiconductor layer (13) is provided in each of the TFTs (5a) as a channel, and an ultraviolet light absorbing layer (22) having a light transmitting property is provided in each of the pixels (P) so as to overlap the oxide semiconductor layer (13).Type: GrantFiled: February 14, 2011Date of Patent: April 15, 2014Assignee: Sharp Kabushiki KaishaInventors: Yoshiyuki Harumoto, Yoshifumi Ohta, Yoshimasa Chikama, Tokuo Yoshida, Masahiko Suzuki, Okifumi Nakagawa, Yoshinobu Miyamoto, Tetsuya Yamashita, Hinae Mizuno
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Patent number: 8685803Abstract: A semiconductor device includes: a thin film transistor having a gate line (3a), a first insulating film (5), an island-shaped oxide semiconductor layer (7a), a second insulating film (9), a source line (13as), a drain electrode (13ad), and a passivation film; and a terminal portion having a first connecting portion (3c) made of the same conductive film as the gate line, a second connecting portion (13c) made of the same conductive film as the source line and the drain electrode, and a third connecting portion (19c) formed on the second connecting portion.Type: GrantFiled: December 3, 2010Date of Patent: April 1, 2014Assignee: Sharp Kabushiki KaishaInventors: Yoshimasa Chikama, Hirohiko Nishiki, Yoshifumi Ohta, Takeshi Hara, Tetsuya Aita, Masahiko Suzuki, Michiko Takei, Okifumi Nakagawa, Yoshiyuki Harumoto, Hinae Mizuno
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Patent number: 8592811Abstract: An active matrix substrate (20a) includes a plurality of pixel electrodes (18a) arranged in a matrix, and a plurality of TFTs (5) each connected to a corresponding one of the pixel electrodes (18a), and each including a gate electrode (11a) provided on an insulating substrate (10a), a gate insulating film (12a) covering the gate electrode (11a), a semiconductor layer (16a) provided on the gate insulating film (12a) and having a channel region (C) overlapping the gate electrode (11a), and a source electrode (15aa) and a drain electrode (15b) of copper or copper alloy provided on the gate insulating film (12a) and separated from each other by the channel region (C) of the semiconductor layer (16a). The semiconductor layer (16a) is formed of an oxide semiconductor and covers the source electrode (15aa) and the drain electrode (15b).Type: GrantFiled: February 14, 2011Date of Patent: November 26, 2013Assignee: Sharp Kabushiki KaishaInventors: Masahiko Suzuki, Yoshimasa Chikama, Yoshifumi Ohta, Tokuo Yoshida, Okifumi Nakagawa, Yoshiyuki Harumoto, Yoshinobu Miyamoto, Tetsuya Yamashita, Hinae Mizuno
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Patent number: 8530899Abstract: The present invention has an object of providing a TFT in which generation of an OFF current is reduced by an efficient manufacturing method. A thin film transistor 100 according to the present invention has a gate electrode 12 formed on a substrate 10, an insulating layer 14 formed on the gate electrode 12, a microcrystalline amorphous silicon layer 18 and an amorphous silicon layer 16 that are formed on the insulating layer 14, a semiconductor layer 20 containing an impurity formed on the amorphous silicon layer 16, and a source electrode 22A and a drain electrode 22B that are formed on the semiconductor layer 20 containing an impurity. The microcrystalline amorphous silicon layer 18 and the semiconductor layer 20 containing an impurity are connected to each other through the amorphous silicon layer 16 without being in direct contact with each other.Type: GrantFiled: December 21, 2010Date of Patent: September 10, 2013Assignee: Sharp Kabushiki KaishaInventors: Yoshiyuki Harumoto, Takeshi Hara, Tohru Okabe, Takeshi Yaneda, Tetsuya Aita, Tsuyoshi Inoue, Michiko Takei
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Publication number: 20130207114Abstract: An active matrix substrate (20a) includes a plurality of pixel electrodes (18a) arranged in a matrix, and a plurality of TFTs (5) each connected to a corresponding one of the pixel electrodes (18a), and each including a gate electrode (11a) provided on an insulating substrate (10a), a gate insulating film (12a) covering the gate electrode (11a), a semiconductor layer (16a) provided on the gate insulating film (12a) and having a channel region (C) overlapping the gate electrode (11a), and a source electrode (15aa) and a drain electrode (15b) of copper or copper alloy provided on the gate insulating film (12a) and separated from each other by the channel region (C) of the semiconductor layer (16a). The semiconductor layer (16a) is formed of an oxide semiconductor and covers the source electrode (15aa) and the drain electrode (15b).Type: ApplicationFiled: February 14, 2011Publication date: August 15, 2013Inventors: Masahiko Suzuki, Yoshimasa Chikama, Yuuji Mizuno, Hinae Mizuno, Yoshifumi Ohta, Tokuo Yoshida, Okifumi Nakagawa, Yoshiyuki Harumoto, Yoshinobu Miyamoto, Tetsuya Yamashita
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Publication number: 20130193430Abstract: The present invention provides an oxide semiconductor that realizes a TFT excellent in electric properties and process resistance, a TFT comprising a channel layer formed of the oxide semiconductor, and a display device equipped with the TFT. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor, wherein the oxide semiconductor contains Ga (gallium), In (indium), Zn (zinc), and O (oxygen) as constituent atoms, and the oxide semiconductor has Zn atomic composition satisfying the equation of 0.01?Zn/(In+Zn)?0.22.Type: ApplicationFiled: March 29, 2010Publication date: August 1, 2013Applicant: Sharp Kabushiki KaishaInventors: Yoshifumi Ota, Hirohiko Nishiki, Yoshimasa Chikama, Takeshi Hara, Tetsuya Aita, Masahiko Suzuki, Okifumi Nakagawa, Kazuo Nakagawa, Michiko Takei, Yoshiyuki Harumoto, Hinae Mizuno
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Publication number: 20130140552Abstract: A semiconductor device (100) according to the present invention includes: an oxide semiconductor layer (31) formed on an insulating layer (21), the oxide semiconductor layer (31) containing at least one element selected from the group consisting of In, Zn, and Sn; first and second sacrificial layers (41a) and (41b) formed, with an interspace from each other, on the oxide semiconductor layer (31); a second electrode (52a) formed in contact with an upper face of the first sacrificial layer (41a) and an upper face of the oxide semiconductor layer (31); and a third electrode (52b) formed in contact with an upper face of the second sacrificial layer (41b) and an upper face of the oxide semiconductor layer (31). The first and second sacrificial layers (41a) and (41b) contain an oxide having at least one element selected from the group consisting of Zn, Ga, Mg, Ca, and Sr.Type: ApplicationFiled: February 22, 2011Publication date: June 6, 2013Applicant: SHARP KABUSHIKI KAISHAInventors: Hirohiko Nishiki, Yoshimasa Chikama, Tetsuya Aita, Masahiko Suzuki, Michiko Takei, Okifumi Nakagawa, Yoshiyuki Harumoto, Yoshifumi Ohta, Takeshi Hara, Hinae Mizuno
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Publication number: 20130134411Abstract: A semiconductor device (100A) according to the present invention includes an oxide semiconductor layer (31a), first and second source electrodes (52a1 and 52a2), and first and second drain electrodes (53a1 and 53a2). The second source electrode (52a2) is formed to be in contact with a top surface of the first source electrode and inner to the first source electrode (52a1). The second drain electrode (53a2) is formed to be in contact with a top surface of the first drain electrode (53a1) and inner to the first drain electrode (53a1). The oxide semiconductor layer (31a) is formed to be in contact with the top surface of the first source electrode (52a1) and the top surface of the first drain electrode (53a1).Type: ApplicationFiled: April 5, 2011Publication date: May 30, 2013Applicant: SHARP KABUSHIKI KAISHAInventors: Okifumi Nakagawa, Yoshifumi Ohta, Yoshimasa Chikama, Tsuyoshi Inoue, Masahiko Suzuki, Michiko Takei, Yoshiyuki Harumoto, Yoshinobu Miyamoto, Hinae Mizuno
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Patent number: 8441016Abstract: Disclosed is a high-quality, efficiently manufacturable thin film transistor in which leakage current is minimized. The thin film transistor is provided with a semiconductor layer (34) that contains a channel region (34C) having a microcrystalline semiconductor; source and drain contact layers (35S and 35D) that contains impurities; a first source metal layer (36S) and a first drain metal layer (36D), and a second source metal layer (37S) and a second drain metal layer (37D). The end portion of the second metal source layer (37S) is located at a position receded from the end portion of the first metal source layer (36S) and the end portion of the second drain metal layer (37D) is located at a position receded from the end portion of the first drain metal layer (36D). The semiconductor layer (34) contains low concentration impurity diffusion regions formed near the end portions of the aforementioned source contact layer (35S) and drain contact layer (35D).Type: GrantFiled: July 8, 2010Date of Patent: May 14, 2013Assignee: Sharp Kabushiki KaishaInventors: Tsuyoshi Inoue, Tohru Okabe, Tetsuya Aita, Michiko Takei, Yoshiyuki Harumoto, Takeshi Yaneda