Patents by Inventor Yoshiyuki Ishigaki
Yoshiyuki Ishigaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180040365Abstract: A semiconductor device which suppresses soft errors and functions as a non-volatile memory and a method for manufacturing the same. In the semiconductor device, a first non-volatile memory element and a second non-volatile memory element are electrically coupled to a first memory node and a second memory node through a first MOS transistor and a second MOS transistor respectively. A first capacitor and a second capacitor each have a storage node electrically coupled to the first memory node and the second memory node respectively and each have a cell plate to form a capacitance between the storage node and the cell plate.Type: ApplicationFiled: June 23, 2017Publication date: February 8, 2018Applicant: Renesas Electronics CorporationInventors: Yukio MAKI, Yoshiyuki ISHIGAKI, Toshiaki TAI, Hideaki YAMAKOSHI, Toshihiko HIROSE, Takuya ISHIDA
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Patent number: 9312267Abstract: In a memory cell array region and a source contact region defined in a surface of a semiconductor substrate, a memory cell transistor including a floating gate electrode and a control gate electrode is formed. In a gate contact region, a dummy floating gate electrode is arranged to partially be superimposed on a dummy element formation region in a two-dimensional view. In a first interlayer insulating film and a second interlayer insulating film covering the memory cell transistor, a contact plug is formed to penetrate the first interlayer insulating film and a via is formed to penetrate a second interlayer insulating film.Type: GrantFiled: July 23, 2015Date of Patent: April 12, 2016Assignee: Renesas Electronics CorporationInventor: Yoshiyuki Ishigaki
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Publication number: 20160049415Abstract: In a memory cell array region and a source contact region defined in a surface of a semiconductor substrate, a memory cell transistor including a floating gate electrode and a control gate electrode is formed. In a gate contact region, a dummy floating gate electrode is arranged to partially be superimposed on a dummy element formation region in a two-dimensional view. In a first interlayer insulating film and a second interlayer insulating film covering the memory cell transistor, a contact plug is formed to penetrate the first interlayer insulating film and a via is formed to penetrate a second interlayer insulating film.Type: ApplicationFiled: July 23, 2015Publication date: February 18, 2016Inventor: Yoshiyuki ISHIGAKI
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Patent number: 8908419Abstract: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.Type: GrantFiled: March 18, 2013Date of Patent: December 9, 2014Assignee: Renesas Electronics CorporationInventors: Hidemoto Tomita, Shigeki Ohbayashi, Yoshiyuki Ishigaki
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Publication number: 20130234256Abstract: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.Type: ApplicationFiled: March 18, 2013Publication date: September 12, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hidemoto TOMITA, Shigeki OHBAYASHI, Yoshiyuki ISHIGAKI
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Patent number: 8422274Abstract: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.Type: GrantFiled: November 15, 2011Date of Patent: April 16, 2013Assignee: Renesas Electronics CorporationInventors: Hidemoto Tomita, Shigeki Ohbayashi, Yoshiyuki Ishigaki
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Patent number: 8395932Abstract: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.Type: GrantFiled: June 30, 2010Date of Patent: March 12, 2013Assignee: Renesas Electronics CorporationInventors: Hidemoto Tomita, Shigeki Ohbayashi, Yoshiyuki Ishigaki
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Publication number: 20120063213Abstract: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.Type: ApplicationFiled: November 15, 2011Publication date: March 15, 2012Applicant: Renesas Electronics CorporationInventors: Hidemoto Tomita, Shigeki Ohbayashi, Yoshiyuki Ishigaki
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Publication number: 20100265752Abstract: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.Type: ApplicationFiled: June 30, 2010Publication date: October 21, 2010Applicant: Renesas Technology Corp.Inventors: Hidemoto TOMITA, Shigeki Ohbayashi, Yoshiyuki Ishigaki
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Publication number: 20100044773Abstract: To provide a semiconductor memory device having an improved write efficiency because deterioration of a gate insulating film is suppressed. An element formation region is formed in a region of a semiconductor substrate sandwiched between element isolation regions. In the element isolation regions, a silicon oxide film is filled in a trench having a predetermined depth. An erase gate electrode is formed in the element isolation region while being buried in the silicon oxide film. Over the element formation region, floating gate electrodes are formed via a gate oxide film and control gate electrodes are formed over the floating gate electrodes via an ONO film. Two adjacent floating gate electrodes have therebetween an insulating film formed to cover the erase gate electrode.Type: ApplicationFiled: June 30, 2009Publication date: February 25, 2010Inventors: Yoshiyuki Ishigaki, Naoki Tsuji, Hisakazu Otoi, Hiroki Mukai, Yuichi Kunori
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Publication number: 20090034317Abstract: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.Type: ApplicationFiled: September 24, 2008Publication date: February 5, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Hidemoto TOMITA, Shigeki Ohbayashi, Yoshiyuki Ishigaki
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Patent number: 7321152Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.Type: GrantFiled: August 4, 2006Date of Patent: January 22, 2008Assignee: Renesas Technology Corp.Inventors: Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Il-Jung Kim, Kazuhito Tsutsumi, Hirotada Kuriyama, Yoshiyuki Ishigaki, Motomu Ukita, Toshiaki Tsutsumi
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Publication number: 20070177416Abstract: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.Type: ApplicationFiled: March 23, 2007Publication date: August 2, 2007Applicant: RENESAS TECHNOLOGY CORP.Inventors: Hidemoto Tomita, Shigeki Ohbayashi, Yoshiyuki Ishigaki
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Patent number: 7187040Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.Type: GrantFiled: March 14, 2005Date of Patent: March 6, 2007Assignee: Renesas Technology Corp.Inventors: Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Il-Jung Kim, Kazuhito Tsutsumi, Hirotada Kuriyama, Yoshiyuki Ishigaki, Motomu Ukita, Toshiaki Tsutsumi
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Publication number: 20060267012Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.Type: ApplicationFiled: August 4, 2006Publication date: November 30, 2006Applicant: Renesas Technology Corp.Inventors: Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Il-Jung Kim, Kazuhito Tsutsumi, Hirotada Kuriyama, Yoshiyuki Ishigaki, Motomu Ukita, Toshiaki Tsutsumi
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Patent number: 7112854Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.Type: GrantFiled: May 2, 1997Date of Patent: September 26, 2006Assignee: Renesas Technology CorporationInventors: Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Il-Jung Kim, Kazuhito Tsutsumi, Hirotada Kuriyama, Yoshiyuki Ishigaki, Motomu Ukita, Toshiaki Tsutsumi
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Publication number: 20060194390Abstract: A semiconductor device includes an interlayer insulation film including an air gap between portions of adjacent wiring layers or isolation pattern layers or both that are distanced from each other by thinning a layered structure of each of the wiring layers or the isolation pattern layers or both selectively from a top layer to a substrate so that the portions of the wiring layers or the isolation pattern layers or both are distanced from each other.Type: ApplicationFiled: February 16, 2006Publication date: August 31, 2006Inventors: Yutaka Imai, Yoshiyuki Ishigaki
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Publication number: 20060125024Abstract: To improve reliability of FETs having element isolation regions for electrically isolating field effect transistors adjacent to each other in the gate length direction in a mask ROM region, the isolation regions are each constructed by field plate isolation formed simultaneously with gate electrodes of the field effect transistors. This relatively lessens a stress generated in an active region ACT sandwiched by the element isolation regions even if the isolation width of each element isolation region is made relatively small, specifically, less than 0.3 ?m. It is therefore possible to relax or prevent the generation of crystal defects resulting from the stress, thereby reducing occurrence of an undesired leak current between the source and drain of each field effect transistor.Type: ApplicationFiled: December 9, 2005Publication date: June 15, 2006Inventor: Yoshiyuki Ishigaki
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Patent number: 6936878Abstract: A semiconductor memory device includes a memory cell, and first and second capacitive elements. The memory cell has a pair of inverters each including first and second driver nMOS transistors and first and second TFTs, and first and second access nMQS transistors. The first and second capacitive elements is connected to the drain of first and second access nMOS transistors, the drain of first and second driver nMOS transistors, and the drain of first and second TFTs. The gate width of first and second driver nMOS transistors is set at most 1.2 times longer than the gate width of first and second access nMOS transistors.Type: GrantFiled: July 25, 2003Date of Patent: August 30, 2005Assignee: Renesas Technology Corp.Inventors: Yasushi Nakashima, Takashi Izutsu, Yoshiyuki Ishigaki
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Publication number: 20050167673Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.Type: ApplicationFiled: March 14, 2005Publication date: August 4, 2005Applicant: Renesas Technology Corp.Inventors: Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Il-Jung Kim, Kazuhito Tsutsumi, Hirotada Kuriyama, Yoshiyuki Ishigaki, Motomu Ukita, Toshiaki Tsutsumi