Abstract: Problem: To provide a method for manufacturing metal staple fibers that allows for the efficient manufacture of uniform metal staple fibers. Solution: A method for manufacturing metal staple fibers including a cutting step of cutting a metal fiber bundle coated with a fluorine-based polymer into a staple fiber bundle.

Abstract: A semiconductor device manufacture method has the steps of: (a) coating a low dielectric constant low-level insulating film above a semiconductor substrate formed with a plurality of semiconductor elements; (b) processing the low-level insulating film to increase a mechanical strength of the low-level insulating film; (c) coating a low dielectric constant high-level insulating film above the low-level insulating film; and (d) forming a buried wiring including a wiring pattern in the high-level insulating film and a via conductor in the low-level insulating film. The low-level insulating film and high-level insulating film are made from the same material. The process of increasing the mechanical strength includes an ultraviolet ray irradiation process or a hydrogen plasma applying process.

Abstract: A semiconductor device manufacturing method includes forming an insulation film containing silicon, oxygen and carbon over a semiconductor substrate by chemical vapor deposition; making UV cure on the insulation film being heated at a temperature of 350° C. or below after the forming the insulation film; and making helium plasma processing on the insulation film after the UV cure.

Abstract: A semiconductor device manufacturing method includes forming an insulation film containing silicon, oxygen and carbon over a semiconductor substrate by chemical vapor deposition; making UV cure on the insulation film being heated at a temperature of 350° C. or below after the forming the insulation film; and making helium plasma processing on the insulation film after the UV cure.

Abstract: A semiconductor device manufacture method has the steps of: (a) coating a low dielectric constant low-level insulating film above a semiconductor substrate formed with a plurality of semiconductor elements; (b) processing the low-level insulating film to increase a mechanical strength of the low-level insulating film; (c) coating a low dielectric constant high-level insulating film above the low-level insulating film; and (d) forming a buried wiring including a wiring pattern in the high-level insulating film and a via conductor in the low-level insulating film. The low-level insulating film and high-level insulating film are made from the same material. The process of increasing the mechanical strength includes an ultraviolet ray irradiation process or a hydrogen plasma applying process.

Abstract: A method of manufacturing a semiconductor device comprising a wiring structure that includes a vertical wiring section is disclosed. The method comprises a step of forming an interlayer insulation film made of a low dielectric constant material on a wiring layer, a step of forming a silicon oxide film by CVD using SiH4 gas and CO2 gas on the interlayer insulation film, a step of forming a chemically amplified resist film to cover the silicon oxide film, and a step of forming a first opening in a position on the chemically amplified resist film where the vertical wiring section is to be formed.

Abstract: An aspect of the present invention comprises a method of forming holes in a dielectric substrate comprising the steps of applying a layer of photoresist to a dielectric substrate, exposing portions of the photoresist to actinic radiation through a photomask to form a pattern in the photoresist for an array of holes to be etched in the substrate, developing the photoresist, etching the dielectric substrate to form an array of holes, each hole extending at least partially through the dielectric substrate, and removing the excess photoresist. Another aspect of the present invention is a method of simultaneously forming holes in a dielectric substrate some of which extend partially through the substrate and some of which extend completely through the substrate. Other aspects of the present invention are dielectric substrates formed using the methods of the invention.

Abstract: To provide an adhesive composition which can exhibit high adhesion to a circuit board and also has ability capable of releasing the connection to the circuit board connected and reconnecting the circuit board (repairing properties). An adhesive composition comprising: (i) one or more aromatic-group-containing polyhydroxy ether resins, (ii) a compound having an alkoxysilyl group and an imidazole group in the molecule, and (iii) organic particles, wherein the content of the organic particles is 50% by weight or more based on the weight of the adhesive composition.

Abstract: A method of manufacturing a semiconductor device comprising a wiring structure that includes a vertical wiring section is disclosed. The method comprises a step of forming an interlayer insulation film made of a low dielectric constant material on a wiring layer, a step of forming a silicon oxide film by CVD using SiH4 gas and CO2 gas on the interlayer insulation film, a step of forming a chemically amplified resist film to cover the silicon oxide film, and a step of forming a first opening in a position on the chemically amplified resist film where the vertical wiring section is to be formed.

Abstract: The present invention provides a wiring board capable of realizing electrical connectivity even with connection leads having a fine pitch of 100 ?m or less. The present invention relates to a wiring board with adhesive film comprising: a wiring board, in which the surface of a connection terminal portion on the end of a connection lead on the wiring board has a non-flat shape formed by a plating method; and, an adhesive film that covers the surface of the connection terminal portion and contains either a thermoplastic resin or a thermoplastic, thermosetting resin.

Abstract: A semiconductor device manufacture method has the steps of: (a) coating a low dielectric constant low-level insulating film above a semiconductor substrate formed with a plurality of semiconductor elements; (b) processing the low-level insulating film to increase a mechanical strength of the low-level insulating film; (c) coating a low dielectric constant high-level insulating film above the low-level insulating film; and (d) forming a buried wiring including a wiring pattern in the high-level insulating film and a via conductor in the low-level insulating film. The low-level insulating film and high-level insulating film are made from the same material. The process of increasing the mechanical strength includes an ultraviolet ray irradiation process or a hydrogen plasma applying process.

Abstract: A method of manufacturing a semiconductor device comprising a wiring structure that includes a vertical wiring section is disclosed. The method comprises a step of forming an interlayer insulation film made of a low dielectric constant material on a wiring layer, a step of forming a silicon oxide film by CVD using SiH4 gas and CO2 gas on the interlayer insulation film, a step of forming a chemically amplified resist film to cover the silicon oxide film, and a step of forming a first opening in a position on the chemically amplified resist film where the vertical wiring section is to be formed.

Abstract: The method for forming an SiC-based film comprises the step of generating NH3 plasma on the surface of a substrate 20 in a chamber to make NH3 plasma processing on the substrate 20, the step of removing reaction products containing nitrogen remaining in the chamber, and the step of forming an SiC film 34 on the substrate 20 by PECVD.

Abstract: A semiconductor device includes a multilayer interconnection structure including an organic interlayer insulation film in which a conductor pattern is formed by a damascene process, wherein the organic interlayer insulation film carries thereon an organic spin-on-glass film.

Abstract: A semiconductor device includes a multilayer interconnection structure including an organic interlayer insulation film in which a conductor pattern is formed by a damascene process, wherein the organic interlayer insulation film carries thereon an organic spin-on-glass film.

Abstract: A semiconductor device includes a multilayer interconnection structure including an organic interlayer insulation film in which a conductor pattern is formed by a damascene process, wherein the organic interlayer insulation film carries thereon an organic spin-on-glass film.

Abstract: A semiconductor device includes a multilayer interconnection structure including an organic interlayer insulation film in which a conductor pattern is formed by a damascene process, wherein the organic interlayer insulation film carries thereon an organic spin-on-glass film.

Abstract: A semiconductor device includes a porous interlayer insulation film including therein a stacking of SiO2 particles having a diameter in the range between about 5 nm and about 50 nm and stacked so as to form a void between adjacent particles, wherein the interlayer insulation film has a porosity in the range between about 13% and about 42%.

Abstract: A material and a method for planarizing an uneven surface of a substrate, such as those used for making wiring boards and electronic devices and having broad patterns on their surfaces, are provided. The material is a polysilphenylenesiloxane or a copolymer of polysilphenylenesiloxane with an organosiloxane, and is applied to an uneven surface of a substrate, and then heated to be reflowed to thereby be formed into a planarized film or layer. The material allows a substrate containing wiring having a width of up to several hundred micrometers to be planarized.

Abstract: A semiconductor substrate 11 having concavities and convexities in the upper surface, and silica particles (granular insulators) 15 provided in the concavities to planarize the entire upper surface of the semiconductor substrate 11 are included. First, the silica particles 15 are laid over an upper surface of a semiconductor substrate 11 to provide the granular insulators 15 in cavities in the upper surface of the semiconductor substrate 11, and the silica particles 15 provided on convexities on the upper surface of the semiconductor substrate 11 are removed, whereby the concavities 11 are buried with the silica particles 15 so as to improve global planarizarion.