Abstract: A plurality of image recognizing systems which are distributed and arranged and a centralized control apparatus are mutually connected via transmission lines. Each of the image recognizing apparatuses executes a predetermined image process to the image which is input from the ITV camera and transmits the processed image to the centralized control apparatus. The centralized control apparatus forms tuning parameters which are necessary for the instrumentation control by each image recognizing system from the transmitted processed image and transmits the tuning parameters to each image recognizing system. After the tuning parameters are received, each image recognizing system executes the measuring process. Therefore, for a plurality of image recognizing systems which are distributed at remote locations, the instrumentation control of each image recognizing system can be executed by the centralized control apparatus from one position.

Abstract: An information processing apparatus using a neural network learning function has, in one embodiment, a computer system and a pattern recognition apparatus associated with each other via a communication cable. The computer system includes a learning section having a first neural network and serves to adjust the weights of connection therein as a result of learning with a learning data signal supplied thereto from the pattern recognition apparatus via the communication cable. The pattern recognition apparatus includes an associative output section having a second neural network and receives data on the adjusted weights from the learning section via the communication cable to reconstruct the second neural network with the data on the adjusted weights. The pattern recognition apparatus with the associative output section having the reconstructed second neural network performs pattern recognition independently of the computer system with the communication cable being brought into an electrical isolation mode.

Abstract: An LSI parallel image processor in which line buffers and data-flow switching circuits each requiring a larger amount of hardware in the prior art are incorporated into an LSI circuit, the image data delayed by the line buffers is output from an image data output port, shift registers each having a variable number of steps for preserving local image regions are intermittently shifted-in in accordance with applied clocks, and the contents of the shift registers are sequentially read out.

Abstract: An information processing apparatus using a neural network learning function has, in one embodiment, a computer system and a pattern recognition apparatus associated with each other via a communication cable. The computer system includes a learning section having a first neural network and serves to adjust the weights of connection therein as a result of learning with a learning data signal supplied thereto from the pattern recognition apparatus via the communication cable. The pattern recognition apparatus includes an associative output section having a second neural network and receives data on the adjusted weights from the learning section via the communication cable to reconstruct the second neural network with the data on the adjusted weights. The pattern recognition apparatus with the associative output section having the reconstructed second neural network performs pattern recognition independently of the computer system with the communication cable being brought into an electrical isolation mode.

Abstract: A multifunctional image processor capable of executing a variety of image processing functions such as a spatial convolution and a color image processing at a higher speed includes an image data distribute unit for distributing the gray-scale and color image data externally supplied by use of programs in accordance with the operation of the image processing and a parallel image data processing unit for conducting a parallel operation on distributed image data in accordance with the operation of the image processing.

Abstract: A high speed, multi-function and expandable image processing LSI (image signal processor) for realizing a gray level image processing technique is disclosed. The architecture of the image signal processor can process a gray level image having 256 tones at a video rate (256.times.256 image, 6 MHz, non-interlace), allows expansion of a partial operation area (kernel) and can carry out various partial neighborhood operations. The image signal processor is a partial parallel type image processing LSI which carries out a parallel operation by using the same number of processor elements as that of input pixel data used to produce one output pixel of data.