Patents by Inventor Yoshiyuki Yoneda
Yoshiyuki Yoneda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240092337Abstract: A vehicle control apparatus includes front-wheel and rear-wheel driving systems, and a control system. The front-wheel driving system includes a first travel motor mechanically coupled to a front wheel of a vehicle and a first accumulator electrically coupled to the first travel motor. The rear-wheel driving system includes a second travel motor mechanically coupled to a rear wheel of the vehicle and a second accumulator electrically coupled to the second travel motor. The control system includes one or more processors and one or more memories communicably coupled to the one or more processors, and controls the first and second travel motors. When a difference between an SOC of the first accumulator and an SOC of the second accumulator is greater than a threshold value, the one or more processors change a torque distribution ratio between the first and second travel motors from a reference distribution ratio.Type: ApplicationFiled: September 13, 2023Publication date: March 21, 2024Inventors: Hiroshi KUSANO, Yoshinobu YAMAZAKI, Masami OGURI, Akihiro NABESHIMA, Yoshiyuki JIN, Takeshi YONEDA, Fumiya SATO, Keigo YAMADA, Takumi ARAKI, Shuntaro MIURA
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Patent number: 9076789Abstract: A semiconductor device is disclosed that includes a support substrate, a first semiconductor element that is mounted on one side of the support substrate, a second semiconductor element including a high frequency electrode that is mounted on the one side of the support substrate, a via hole that is provided at the support substrate in relation to the high frequency electrode, and an external connection electrode that is provided on the other side of the support substrate in relation to the via hole.Type: GrantFiled: January 6, 2014Date of Patent: July 7, 2015Assignee: SOCIONEXT INC.Inventors: Yoshitaka Aiba, Tetsuya Fujisawa, Yoshiyuki Yoneda
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Patent number: 9041186Abstract: Disclosed is a semiconductor device including first and second semiconductor elements, first and second external connection terminals and a sealing member. The first external connection terminal is provided at a first surface of the first semiconductor element. The second semiconductor element is provided at a second surface side, that is at a side opposite to the first surface, of the first semiconductor element. The second external connection terminal is connected to the second semiconductor element, and the second external connection terminal is configured to be, together with the first external connection terminal, connected to a wiring board. The sealing member seals the first and second semiconductor elements and exposes a portion, that is configured to be connected to the wiring board, of the first external connection terminal and a portion, that is configured to be connected to the wiring board, of the second external connection terminal.Type: GrantFiled: March 22, 2013Date of Patent: May 26, 2015Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Ryuji Nomoto, Yoshiyuki Yoneda, Koichi Nakamura
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Patent number: 8759119Abstract: A semiconductor device has an alignment mark which can be recognized by a conventional wafer prober. A redistribution layer connects electrodes of the semiconductor device to electrode pads located in predetermined positions of the redistribution layer. Metal posts configured to be provided with external connection electrodes are formed on the electrode pads of the redistribution layer. A mark member made of the same material as the metal posts is formed on the redistribution layer. The mark member serves as an alignment mark located in a predetermined positional relationship with the metal posts.Type: GrantFiled: February 26, 2013Date of Patent: June 24, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Shigeyuki Maruyama, Yasuyuki Itoh, Tetsurou Honda, Kazuhiro Tashiro, Makoto Haseyama, Kenichi Nagashige, Yoshiyuki Yoneda, Hirohisa Matsuki
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Publication number: 20140117562Abstract: A semiconductor device is disclosed that includes a support substrate, a first semiconductor element that is mounted on one side of the support substrate, a second semiconductor element including a high frequency electrode that is mounted on the one side of the support substrate, a via hole that is provided at the support substrate in relation to the high frequency electrode, and an external connection electrode that is provided on the other side of the support substrate in relation to the via hole.Type: ApplicationFiled: January 6, 2014Publication date: May 1, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Yoshitaka Aiba, Tetsuya Fujisawa, Yoshiyuki Yoneda
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Publication number: 20130299845Abstract: Disclosed is a semiconductor device including first and second semiconductor elements, first and second external connection terminals and a sealing member. The first external connection terminal is provided at a first surface of the first semiconductor element. The second semiconductor element is provided at a second surface side, that is at a side opposite to the first surface, of the first semiconductor element. The second external connection terminal is connected to the second semiconductor element, and the second external connection terminal is configured to be, together with the first external connection terminal, connected to a wiring board. The sealing member seals the first and second semiconductor elements and exposes a portion, that is configured to be connected to the wiring board, of the first external connection terminal and a portion, that is configured to be connected to the wiring board, of the second external connection terminal.Type: ApplicationFiled: March 22, 2013Publication date: November 14, 2013Inventors: Ryuji Nomoto, Yoshiyuki Yoneda, Koichi Nakamura
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Patent number: 8404496Abstract: A semiconductor device has an alignment mark which can be recognized by a conventional wafer prober. A redistribution layer connects electrodes of the semiconductor device to electrode pads located in predetermined positions of the redistribution layer. Metal posts configured to be provided with external connection electrodes are formed on the electrode pads of the redistribution layer. A mark member made of the same material as the metal posts is formed on the redistribution layer. The mark member serves as an alignment mark located in a predetermined positional relationship with the metal posts.Type: GrantFiled: May 24, 2006Date of Patent: March 26, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Shigeyuki Maruyama, Yasuyuki Itoh, Tetsurou Honda, Kazuhiro Tashiro, Makoto Haseyama, Kenichi Nagashige, Yoshiyuki Yoneda, Hirohisa Matsuki
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Publication number: 20130065882Abstract: This invention relates to a VLA-4 inhibitory drug, having good oral absorbability and exhibiting sufficient anti-inflammatory effects when administered orally, wherein an active ingredient is represented by formula (I), or a salt thereof: Q represents an optionally-substituted monocyclic or bicyclic nitrogen-containing heterocyclic group having a nitrogen atom as the bonding site; Y represents an oxygen atom or CH2; W represents an optionally-substituted bicyclic aromatic hydrocarbon ring group or an optionally-substituted bicyclic aromatic heterocyclic group; A1 represents a nitrogen atom or C—R3d wherein R3d represents a hydrogen atom, a halogen atom, a C1-8 alkoxy group or a C1-8 alkyl group; R1 represents H or a C1-8 alkyl group; R2 represents H, a halogen, a C1-8 alkoxyType: ApplicationFiled: October 3, 2012Publication date: March 14, 2013Inventors: Nobuo Machinaga, Shin Iimura, Yoshiyuki Yoneda, Jun Chiba, Fumihito Muro, Hideko Hoh, Atsushi Nakayama
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Publication number: 20120157437Abstract: This invention relates to a VLA-4 inhibitory drug, having good oral absorbability and exhibiting sufficient anti-inflammatory effects when administered orally, wherein an active ingredient is represented by formula (I), or a salt thereof: Q represents an optionally-substituted monocyclic or bicyclic nitrogen-containing heterocyclic group having a nitrogen atom as the bonding site; Y represents an oxygen atom or CH2; W represents an optionally-substituted bicyclic aromatic hydrocarbon ring group or an optionally-substituted bicyclic aromatic heterocyclic group; A1 represents a nitrogen atom or C—R3d wherein R3d represents a hydrogen atom, a halogen atom, a C1-8 alkoxy group or a C1-8 alkyl group; R1 represents H or a C1-8 alkyl group; R2 represents H, a halogen, a C1-8 alkoxy group, or an optionally-substituted benzyloxy group; and R3a, R3b and R3c independently represent H, a halogen atom, a C1-8 alkoxy group or a C1-8 alkyl group.Type: ApplicationFiled: February 1, 2012Publication date: June 21, 2012Applicant: DAIICHI SANKYO COMPANY, LIMITEDInventors: Nobuo MACHINAGA, Shin Ilmura, Yoshiyuki Yoneda, Jun Chiba, Fumihito Muro, Hideko Hoh, Atsushi Nakayama
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Patent number: 8129366Abstract: There is provided a VLA-4 inhibitory drug having good oral absorbability and exhibiting sufficient anti-inflammatory effects when administered orally.Type: GrantFiled: December 13, 2006Date of Patent: March 6, 2012Assignee: Daiichi Sankyo Company, LimitedInventors: Nobuo Machinaga, Shin Iimura, Yoshiyuki Yoneda, Jun Chiba, Fumihito Muro, Hideko Hoh, Atsushi Nakayama
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Patent number: 8097954Abstract: A semiconductor device of the invention includes a substrate in which a power-supply electrode and a ground electrode are provided. A first semiconductor chip is disposed over the substrate and has a first conductor layer formed on a surface facing a second semiconductor chip. A second conductor layer is disposed over the first semiconductor chip and has a second conductor layer formed on a surface facing the first semiconductor chip. And an adhesive layer is disposed between the first conductor layer and the second conductor layer and bonds together the first semiconductor chip and the second semiconductor chip. In the semiconductor device, the adhesive layer and the first and second conductor layers function as a capacitor.Type: GrantFiled: August 23, 2006Date of Patent: January 17, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Kaname Ozawa, Mitsutaka Sato, Yoshiyuki Yoneda
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Patent number: 7754534Abstract: A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.Type: GrantFiled: April 21, 2008Date of Patent: July 13, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Nobukatsu Saito, Masaharu Minamizawa, Yoshiyuki Yoneda, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Tadahiro Okamoto, Eiji Watanabe
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Publication number: 20100076202Abstract: The present invention provides an advantageous method for producing an intermediate which is useful for production of a compound which exhibits excellent VLA-4 inhibitory effect and safety. An intermediate (14) is produced through the following reaction scheme.Type: ApplicationFiled: December 1, 2009Publication date: March 25, 2010Applicant: DAIICHI PHARMACEUTICAL CO., LTD.Inventors: Yoshihiro TAKAYANAGI, Toshihide Yamada, Yukito Furuya, Yoshiyuki Yoneda
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Publication number: 20090233901Abstract: There is provided a VLA-4 inhibitory drug having good oral absorbability and exhibiting sufficient anti-inflammatory effects when administered orally.Type: ApplicationFiled: December 13, 2006Publication date: September 17, 2009Applicant: Daiichi Sankyo Company, LimitedInventors: Nobuo Machinaga, Shin Iimura, Yoshiyuki Yoneda, Jun Chiba, Fumihito Muro, Hideko Hoh, Atsushi Nakayama
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Publication number: 20080261336Abstract: A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.Type: ApplicationFiled: April 21, 2008Publication date: October 23, 2008Applicant: FUJITSU LIMITEDInventors: Nobukatsu Saito, Masaharu Minamizawa, Yoshiyuki Yoneda, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Tadahiro Okamoto, Eiji Watanabe
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Publication number: 20080174001Abstract: A semiconductor device is disclosed that includes a support substrate, a first semiconductor element that is mounted on one side of the support substrate, a second semiconductor element including a high frequency electrode that is mounted on the one side of the support substrate, a via hole that is provided at the support substrate in relation to the high frequency electrode, and an external connection electrode that is provided on the other side of the support substrate in relation to the via hole.Type: ApplicationFiled: March 13, 2008Publication date: July 24, 2008Applicant: FUJITSU LIMITEDInventors: Yoshitaka Aiba, Tetsuya Fujisawa, Yoshiyuki Yoneda
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Patent number: 7345179Abstract: This invention provides an industrially useful process for producing 1,4-transcyclohexanecarboxylic acid derivative (1) which has excellent VLA-4 inhibitory action and safety, and an intermediate which is useful in such method.Type: GrantFiled: May 7, 2004Date of Patent: March 18, 2008Assignee: Daiichi Pharmaceutical Co., Ltd.Inventors: Atsushi Nakayama, Nobuo Machinaga, Yoshiyuki Yoneda, Masaki Setoguchi
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Publication number: 20070232601Abstract: An object of the present invention is to provide a compound which selectively inhibits binding of a ligand and ?4?1 integrin (VLA-4), a process for producing the compound, and a medicament containing the compound. A compound represented by the formula (I) etc. or a salt thereof, a process for producing the compound or a salt thereof, a medicament containing the compound or a salt thereof, as well as a preventive and/or a therapeutic agent for a disease caused by cell adhesion, for example, inflammatory reaction, autoimmune disease, cancer metastasis, bronchial asthma, nasal obstruction, diabetes, arthritis, psoriasis, multiple sclerosis, inflammatory bowel disease and rejection reaction at transplantation, containing the compound or a salt thereof as a primary component. [wherein Y1 represents a divalent aryl group etc., V1 represents an aryl group etc., and R11 to R14 represent H, OH or a halogen atom etc.Type: ApplicationFiled: June 14, 2005Publication date: October 4, 2007Inventors: Yoshiyuki Yoneda, Atsushi Nakayama, Nobuo Machinaga, Jun Chiba, Fumihito Muro
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Patent number: 7251801Abstract: A method of design of a circuit board enabling high density conductor lines to be drawn efficiently. A rats nest is formed by connecting pads to which terminals of an electronic device are connected and external connection terminals by lines. A region with the highest density of lines of the rats nest is then selected and design rules relating to routes and dimensions of conductor lines are set in the region with the highest density of lines of the rats nest. Conductor lines are then laid at the region with the highest density of lines of the rats nest, and whether or not the conductor lines can be laid at the region with the highest density of lines of the rats nest is confirmed. Setting of the design rules and laying of conductor lines are if the conductor lines cannot be laid, and the conductor lines of the remaining regions are laid by the set design rules if the conductor lines can be laid.Type: GrantFiled: December 23, 2004Date of Patent: July 31, 2007Assignee: Fujitsu LimitedInventors: Kaname Ozawa, Mitsutaka Sato, Tetsuya Fujisawa, Yoshiyuki Yoneda, Ryuji Nomoto, Yoshitaka Aiba
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Publication number: 20070149607Abstract: The present invention provides an advantageous method for producing an intermediate which is useful for production of a compound which exhibits excellent VLA-4 inhibitory effect and safety. An intermediate (14) is produced through the following reaction scheme.Type: ApplicationFiled: December 27, 2004Publication date: June 28, 2007Applicant: DAICHI PAHARMACEUTICAL CO., LTD.Inventors: Yoshihiro Takayanagi, Toshihide Yamada, Yukito Furuya, Yoshiyuki Yoneda