Abstract: A method for optimizing a verification regression includes obtaining data, by a processor, of previously executed runs of at least one verification regression session; extracting from the data, by the processor, values of one or a plurality of control knobs and values of one or a plurality verification metrics that were recorded during the execution for each of the previously executed runs of said at least one verification regression; finding, by the processor, correlation between said one or a plurality of the control knobs and each said one or a plurality of verification metrics, and generating a set of one or a plurality of control conditions based on the found correlation; and applying, by the processor, the generated set of one or a plurality of control conditions on the verification environment or on the DUT, or on both, to obtain a new verification regression session.

Abstract: A method and a system for converting a variable delay in real number modeling code to cycle-driven simulation interface event for digital/mixed signal emulation is provided. The method comprises identifying a variable delay of an analog signal in real number modeling code defining an analog circuit; determining a frequency and a maximum number of cycles for a series of discrete clock cycles, wherein the variable delay corresponds to one cycle in the series of discrete clock cycles; converting the variable delay into a plurality of cycle-driven discrete events based on the series of discrete clock cycles; and generating synthesizable code based on the plurality of cycle-driven discrete events for digital mixed signal emulation. A system and a non-transitory computer readable medium to perform the above method are also provided.

Abstract: A method including receiving a first configuration of a device validated against a design constraint, is provided. A configuration includes stimuli controls and stimuli parameters used as inputs in a device model. The method includes determining a quality of the first configuration based on an estimation of an output parameter including a desired behavior of the device, simulating the device in the first configuration when the first configuration quality overcomes a threshold, and requesting a second configuration of the device when the quality of the first configuration is below the selected threshold. The method also includes obtaining a regression based on multiple, high quality configurations to determine, for the device, a distribution of output parameter values and comparing the distribution of output parameter values with a baseline of a random regression to adjust the machine learning engine according to a target range of output parameter values.

Abstract: A method including selecting multiple input parameters of a device configuration environment to perform multiple simulations on an electronic device defined by the device configuration environment is provided. The method with multiple values for the multiple input parameters and a value of an output parameter resulting from the multiple simulations, and extracting a distribution of output parameter values and a distribution of input parameter values from a database. The method also includes finding a correlation involving the multiple input parameters and the output parameter based on a target range of the output parameter, and identifying an expected value of the output parameter using a range of values of the multiple input parameters in the correlation involving the multiple input parameters and the output parameter. A system and a nontransitory, computer-readable medium including instructions to perform the above method are also provided.

Abstract: A method including evaluating a configuration of a device for a selected device parameter and determining a value of the selected device parameter in a first optimal configuration that improves a performance of the device is provided. The method includes determining a sensitivity of the performance of the device relative to the value of the selected device parameter and determining a performance metric that differentiates the first optimal configuration with a second optimal configuration based on the sensitivity of the performance of the device. The method includes ranking the first optimal configuration and the second optimal configuration based on the performance metric and simulating the performance of the device with a second device parameter in one of the first optimal configuration or the second optimal configuration, based on the ranking. A system and a computer readable medium to perform the above method are also provided.

Abstract: A method for converting real number modeling to cycle-driven simulation interface file is provided. The method includes verifying an input in a file that includes a real number modeling code, cleaning the real number modeling code in the file, converting the file to a cycle-driven simulation interface file, and verifying the cycle-driven simulation interface file. Converting the method includes building a definitions file storing a width of at least one real number in the circuit design, and selecting a real number modeling file from the circuit design. For the real number modeling file, the method includes parsing the real number modeling file, building a header file associated with the real number modeling file, and building a compilation file associated with the cycle-driven simulation interface file. A system and a non-transitory, computer readable medium to perform the above method are also provided.

Abstract: A method for converting real number modeling to a cycle-driven simulation interface file is provided. The method includes verifying an input in a file that includes a real number modeling code, requesting a user input parameter, converting the file to a cycle-driven simulation interface file based on the user input parameter, and verifying the cycle-driven simulation interface file. Converting the method includes building a definitions file storing a width of at least one real number in the circuit design, and selecting a real number modeling file from the circuit design. For the real number modeling file, the method includes parsing the real number modeling file, building a header file associated with the real number modeling file, and building a compilation file associated with the cycle-driven simulation interface file. A system and a computer readable medium to perform the above method are also provided.

Abstract: A method including receiving source code for controlling a system on a chip and correlating a datum and an instruction in the source code with a first node is provided. The method includes associating the first node with a resource used by the datum and the instruction, based on a model for the system on a chip, illustrating a link between the first node and a second node, indicative of a data dependency in the source code between the first node and the second node, and evaluating a performance of the system on a chip controlled by the source code. Also including forming an annotated source code based on the performance of the system on a chip. A system and a non-transitory, computer-readable medium including instructions to perform the method are also provided.

Abstract: A method for converting a real number modeling to a synthesizable register-transfer level emulation in digital mixed signal environments is provided. The method includes verifying an input in a file including a real number modeling code and cleaning the real number modeling code in the file. The method also includes separating a clean register-transfer level code from the real number modeling code, converting the file to a cycle-driven simulation interface file, and verifying the cycle-driven simulation interface file. The method further includes converting the cycle-driven simulation interface file into a register-transfer level file suitable to perform a circuit emulation in digital mixed signal environments, and verifying that the register-transfer level file is ready to perform circuit emulation in the digital mixed signal environments. A system and a non-transitory, computer readable medium storing commands to perform the above method are also provided.

Abstract: Methods and systems provide creating and reporting of path annotations and renaming a state node using the path annotations for high level synthesis (HLS). In an embodiment, a method to annotate a state node includes identifying labels and pragmas specified in a high-level language input model for wait statements and function calls, and can also accommodate loops. In an embodiment, a method to display and/or report annotation information for a given state node includes displaying a state node name, an associated path annotation, and/or an associated hierarchical path. In an embodiment, a method to rename a state node based on a user-specified name includes using annotation information to locate a target state node and associating the target state node with the user-specified name or an automatically-created name based on the user-specified name. In an embodiment, a name specified for a state node can persist through successive runs of an HLS tool.

Abstract: In one embodiment of the invention, a method of synthesizing a circuit design is disclosed including receiving an input model of an initial circuit design into an electronic design automation system; receiving a user specification detailing a reliability feature to add to the initial circuit design; adding the reliability feature to the input model based upon the user specification to generate a modified input model; and producing an output model of a circuit design with the reliability feature in response to the modified input model.

Abstract: A method of synthesis of multiple implementations of a design is provided comprising: translating a model of the design to a first output model compliant with first constraints; and translating the model of the design to a second output model compliant with second constraints.

Abstract: A method of synthesis of multiple implementations of a design is provided comprising: translating a model of the design to a first output model compliant with first constraints; and translating the model of the design to a second output model compliant with second constraints.

Abstract: A method of synthesis of a model representing a design is provided comprising: inputting to a synthesis tool information representing a design at a level of abstraction; using a synthesis tool to automatically translate the information representing a design at a level of abstraction to a model representing the design at a lower level abstraction; and producing a record the information input to the tool representing the design at the level of abstraction.

Abstract: A method of producing multiple models of a hardware (integrated circuit) design including: translating a master model of a design of the integrated circuit to at least first and second models that are functionally equivalent to the master model and that are at different levels of abstraction from each, other and in which each of the first and second models includes integrated circuit timing information that is accurate for its level of abstraction.

Abstract: A method for analyzing a circuit design identifies a possible noise fault for a timing interval based on a timing analysis of a victim net and at least one aggressor net of the circuit design and determines whether the noise fault is feasible based on a behavioral representation of the victim net and the aggressor net for the timing interval.

Abstract: A method of synthesis of multiple implementations of a design is provided comprising: translating a model of the design to a first output model compliant with first constraints; and translating the model of the design to a second output model compliant with second constraints.

Abstract: A method of producing multiple models of a hardware (integrated circuit) design including: translating a master model of a design of the integrated circuit to at least first and second models that are functionally equivalent to the master model and that are at different levels of abstraction from each, other and in which each of the first and second models includes integrated circuit timing information that is accurate for its level of abstraction.

Abstract: A method of synthesis of a model representing a design is provided comprising: inputting to a synthesis tool information representing a design at a level of abstraction; using a synthesis tool to automatically translate the information representing a design at a level of abstraction to a model representing the design at a lower level abstraction; and producing a record the information input to the tool representing the design at the level of abstraction.