Abstract: A process for building a 3-Dimensional NOR memory array avoids the challenge of etching a conductor material that is aimed at providing local word lines at a fine pitch. The process defines the local word lines between isolation shafts that may be carried out at a lower aspect ratio than would be required for etching the conductor material.

Abstract: A process for building a 3-Dimensional NOR memory array avoids the challenge of etching a conductor material that is aimed at providing local word lines at a fine pitch. The process defines the local word lines between isolation shafts that may be carried out at a lower aspect ratio than would be required for etching the conductor material.

Abstract: A memory device includes source-drain structure bodies and gate structure bodies arranged along a first direction, and global word lines. The source-drain structure body includes a bit line, and first to third semiconductor layers. The first and second semiconductor layers are of first conductivity type and the first semiconductor layer is connected to the bit line. The third semiconductor layer of a second conductivity type contacts the first and second semiconductor layers. The gate structure body includes a local word line and a charge storage film. A first source-drain structure body includes a bit line forming a first reference bit line. A first global word line connects to the local word lines in the gate structure bodies formed on both sides of the first reference bit line and to the local word lines formed in alternate gate structure bodies that are formed between the remaining plurality of source-drain structure bodies.

Abstract: A VNOR memory string includes: (a) first and second pillars embedded in multiple composite layers, each composite layer comprising an insulator layer and a conductor layer, the first and second pillars each comprising a first semiconductor material of a first conductivity; (b) a second semiconductor layer of a second conductivity type opposite the first conductivity type on the outside of third pillar also embedded in the composite layers, the third pillar contacting both the first and second pillars; and (c) a storage layer provided between the second semiconductor layer and each of the conductor layer in the composite layers.

Abstract: A conductor-filled via formed between an interconnection conductor layer and a buried contact above a planar surface of a semiconductor substrate, includes: (a) a first portion that extends from the interconnection conductor layer through a first isolation layer to a step in a staircase structure formed above the buried contacts, wherein (i) the step of the staircase structure is aligned to the buried contact along a first direction substantially normal to the planar surface of the semiconductor substrate, (ii) at the top of the step, the step comprises a bit line layer, a source line layer and a second isolation layer between the bit line layer and the source line layer, and (iii) the first portion electrically contacting the layer at the top of the step; and (b) a second portion extending from a portion of the step below the layer at the top of the step to the buried contact, wherein a spacer insulator lines sidewalls of the conductor-filled via.

Abstract: A process for building a 3-Dimensional NOR memory array avoids the challenge of etching a conductor material that is aimed at providing local word lines at a fine pitch. The process defines the local word lines between isolation shafts that may be carried out at a lower aspect ratio than would be required for etching the conductor material.

Abstract: A semiconductor structure includes a semiconductor device located over a substrate, a dielectric layer stack of at least one first dielectric material layer, a silicon nitride layer, and at least one second dielectric material layer overlying the semiconductor device, and interconnect structures including metallic lines and metallic vias and embedded within the dielectric layer stack. The interconnect structures also include a metal silicide portion that directly contacts the silicon nitride layer. A combination of the silicon nitride layer and the metal silicide portion provides a continuous hydrogen barrier structure that is vertically spaced from the top surface of the semiconductor device.

Abstract: A method of forming a NAND flash memory includes forming a conductive area in a substrate, the conductive area extending along a direction that is perpendicular to the direction along which NAND strings extend, the conductive area connecting terminals of NAND strings. Discrete contact areas in the conductive area are contacted by discrete contact plugs, each contact plug contacting a corresponding contact area in the conductive area.

Abstract: A semiconductor structure includes a semiconductor device located over a substrate, a dielectric layer stack of at least one first dielectric material layer, a silicon nitride layer, and at least one second dielectric material layer overlying the semiconductor device, and interconnect structures including metallic lines and metallic vias and embedded within the dielectric layer stack. The interconnect structures also include a metal silicide portion that directly contacts the silicon nitride layer. A combination of the silicon nitride layer and the metal silicide portion provides a continuous hydrogen barrier structure that is vertically spaced from the top surface of the semiconductor device.

Abstract: A method of forming a NAND flash memory includes forming a conductive area in a substrate, the conductive area extending along a direction that is perpendicular to the direction along which NAND strings extend, the conductive area connecting terminals of NAND strings. Discrete contact areas in the conductive area are contacted by discrete contact plugs, each contact plug contacting a corresponding contact area in the conductive area.