Abstract: A semiconductor device includes a substrate, a channel layer, a first barrier layer, a source/drain contact, and a gate layer. The channel layer is on the substrate. The first barrier layer is on the channel layer and the thickness of the first barrier layer is less than 6 nm. The source/drain contact is on the first barrier layer and is directly contact with the first barrier layer. The gate layer is over the first barrier layer.

Abstract: Present invention is related to a tumor microenvironment on chip or a biochip for cell therapy having a carrier, a first cell or tissue culture area and a second cell or tissue area imbedded within the carrier. The present invention provides a biochip successfully cooperating micro fluidic technology and cell culture achieving the goal for detecting or testing the function of cell therapy for cancer or tumor.

Abstract: A high electron mobility transistor includes a growth substrate, a lattice matching layer, an back-barrier layer, an electron blocking layer, a channel layer, an active layer, a source, a gate, and a drain. The lattice matching layer and the back-barrier layer are formed on the growth substrate. The back-barrier layer includes GaN doped with C. The electron blocking layer is formed on the back-barrier layer. The electron blocking layer includes AlGaN, wherein the doping percent of Al atoms of the AlGaN is 3˜5% and the doping percent of Ga atoms of the AlGaN is 95˜97%. The electron blocking layer has a thickness of 2˜5 nm. The channel layer and the active layer are formed on the electron blocking layer. The source, the gate, and the drain are formed on the active layer.

Abstract: A method includes receiving distillation data including a plurality of out-of-domain training utterances. For each particular out-of-domain training utterance of the distillation data, the method includes generating a corresponding augmented out-of-domain training utterance, and generating, using a teacher ASR model trained on training data corresponding to a target domain, a pseudo-label corresponding to the corresponding augmented out-of-domain training utterance. The method also includes distilling a student ASR model from the teacher ASR model by training the student ASR model using the corresponding augmented out-of-domain training utterances paired with the corresponding pseudo-labels generated by the teacher ASR model.

Abstract: A high electron mobility transistor and a method for fabricating the same is disclosed. Firstly, a lattice matching layer, a channel layer, and an AlGaN layer are sequentially formed on a growth substrate. The AlGaN layer includes a first area, a second area, and a third area, wherein the second area is located between the first area and the third area. Then, an insulation block is formed on the second area of the AlGaN layer and two GaN blocks are respectively formed on the first area and the third area of the AlGaN layer. Two InAlGaN blocks are respectively formed on the GaN blocks and the insulation block is removed. Finally, a gate is formed to interfere the second area of the AlGaN layer and a source and a drain are respectively formed on the InAlGaN blocks.

Abstract: In some embodiments of the present disclosure, a sustained release osmotic-controlled pharmaceutical composition is provided, including: a core and a semi-permeable membrane coated on the core. The core includes a drug compartment, in which the drug compartment includes a first active ingredient, a first polymer and a first osmogen, and the first active ingredient includes lurasidone, a pharmaceutical acceptable salt of the lurasidone or a combination thereof. The semi-permeable membrane includes a membrane body and at least one pore distributed in the membrane body.

Abstract: The disclosure provides a local stretch packaging structure, including a substrate, a flexible electronic element, a plurality of light-emitting display elements, and a packaging layer. The flexible electronic element is disposed on the substrate. These light-emitting display elements are disposed on the flexible electronic element. The packaging layer includes a packaging area and a non-packaging area. The packaging area covers the upper surface and sidewalls of these light-emitting display elements. The non-packaging area is directly covered the flexible electronic element that is not disposed with these light-emitting display elements.

Abstract: The embodiments are directed towards providing personalized federated learning (PFL) models via sharable federated basis models. A model architecture and learning algorithm for PFL models is disclosed. The embodiments learn a set of basis models, which can be combined layer by layer to form a personalized model for each client using specifically learned combination coefficients. The set of basis models are shared with each client of a set of the clients. Thus, the set of basis models is common to each client of the set of clients. However, each client may generate a unique PFL based on their specifically learned combination coefficients. The unique combination of coefficients for each client may be encoded in a separate personalized vector for each of the clients.

Abstract: A champagne tower-type multi-stage throttle control valve includes a valve body, a valve cover, a throttle sleeve, and a valve core. A sleeve cavity of the throttle sleeve is shaped as a stepped hole with two or more layers. The valve core is shaped as a stepped shaft with two or more layers coaxial with the throttle sleeve. The number of shaft shoulders of the valve core is smaller than or equal to the number of hole shoulders of the sleeve cavity of the throttle sleeve, such that each set of shaft shoulders of the valve core in an axial direction can form a sealing surface fit with corresponding hole shoulders of the throttle sleeve. A flow channel groove is axially or obliquely formed on each of the hole shoulders of the throttle sleeve and/or the shaft shoulders of the valve core.

Abstract: A laser automatic compensation control device includes a controller, a digital array, a decoder, a compensation array and a synchronizer. The controller is configured for receiving a number of laser energy signals and comparing each laser energy signal with a corresponding preset energy value to obtain a corresponding output digital signal. The digital array is electrically connected to the controller and configured for storing the output digital signals. The decoder is electrically connected to the digital array and configured for converting the output digital signals into a number of analog compensation signals. The compensation array is electrically connected to the decoder and configured for storing the analog compensation signals. The synchronizer is electrically connected to the compensation array and configured for receiving the analog compensation signals, and synchronously outputting the analog compensation signals to a laser diode array.

Abstract: An identity certificate may be issued to a blockchain node. The issuance may include issuing a first identity certificate to a first terminal and receiving a second identity certificate issuance request that is from the first terminal. A second identity certificate may be issued to the first terminal, and a third identity certificate issuance request is received from the second terminal. A third identity certificate is issued to the second terminal, so that the second terminal forwards the third identity certificate to the third terminal.

Abstract: Systems and methods for generating, distributing, and using performance mode BIOS configurations are disclosed. Each performance mode BIOS configuration can be a unique set of BIOS setting values that have been established to optimize a particular performance parameter or set of performance parameters, such as boot speed or operating system installation speed. Based on a given hardware configuration and/or set of performance parameters, one or more performance mode BIOS configurations can be packaged and transferred to a memory of a BMC in the form of one or more configuration payloads. The BIOS Setup Utility can display all configuration payloads, such as listed by the type of performance mode (e.g., “Boot Speed Performance Mode” and “OS Installation Performance Mode”), that are available in the BMC memory and allow a user to overwrite the memory containing the current BIOS configuration with a selected configuration payload.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: A method includes depositing a first passivation layer over a conductive feature, wherein the first passivation layer has a first dielectric constant, forming a capacitor over the first passivation layer, and depositing a second passivation layer over the capacitor, wherein the second passivation layer has a second dielectric constant greater than the first dielectric constant. The method further includes forming a redistribution line over and electrically connecting to the capacitor, depositing a third passivation layer over the redistribution line, and forming an Under-Bump-Metallurgy (UBM) penetrating through the third passivation layer to electrically connect to the redistribution line.

Abstract: The present disclosure provides a method and a device for preparing a modified poly (m-phenylene isophthalamide) (PMIA) fiber by continuous polymerization-dry-wet spinning. The method includes the following steps: (1) preparing a mixed solution of m-phenylenediamine (MPD) and a copolymerized diamine monomer in N,N-dimethylacetamide (DMAC) serving as a solvent using a cosolvent; (2) mixing isophthaloyl chloride (IPC) with the mixed solution of the MPD and the copolymerized diamine monomer in the DMAC, and conducting pre-polycondensation and polycondensation in sequence to obtain a modified PMIA resin solution; and (3) subjecting the modified PMIA resin solution to additive addition, filtration, defoaming, and dry-wet spinning to obtain the modified PMIA fiber.

Abstract: A chip packaging structure and a chip packaging method are provided. The chip packaging structure includes a first substrate, an image sensing chip, a supporting member, a second substrate, and an encapsulant. The image sensing chip is disposed on an upper surface of the first substrate, and the image sensing chip has an image sensing region. The supporting member is disposed on an upper surface of the image sensing chip and surrounds the image sensing region. The supporting member is formed by stacking microstructures with each other, so that the supporting member has pores. The second substrate is disposed on an upper surface of the supporting member, and the second substrate, the supporting member, and the image sensing chip define an air cavity. The encapsulant is attached to the upper surface of the first substrate and a side surface of the second substrate and filled into the pores.

Abstract: Techniques pertaining to an efficient pre-channel reservation mechanism for target wake time (TWT) and restricted TWT (rTWT) in overlapping basic service set (OBSS) dense networks are described. A first station (STA) transmits a frame to reserve a reservation period. The first STA then communicates with a second STA during the reservation period which aligns at least partially with a target wake time (TWT) service period (SP) or a restricted TWT (rTWT) SP of the second STA.

Abstract: A semiconductor package including one or more dam structures and the method of forming are provided. A semiconductor package may include an interposer, a semiconductor die bonded to a first side of the interposer, an encapsulant on the first side of the interposer encircling the semiconductor die, a substrate bonded to the a second side of the interposer, an underfill between the interposer and the substrate, and one or more of dam structures on the substrate. The one or more dam structures may be disposed adjacent respective corners of the interposer and may be in direct contact with the underfill. The coefficient of thermal expansion of the one or more of dam structures may be smaller than the coefficient of thermal expansion of the underfill.

Abstract: An apparatus for probing a device-under-test (DUT) includes a fixture, a circuitry film attached to the fixture, a probing tip disposed on and electrically coupled to the circuitry film to probe a device-under-test, and a first signal connector disposed on the circuitry film and electrically coupled to the probing tip through the circuitry film. The first signal connector is oriented in a direction that is angularly offset from a lengthwise direction of the probing tip.

Abstract: An inductor device includes first trace, second trace, third trace, fourth trace, first capacitor, and second capacitor. One terminal of each of the at least two sub-traces of first trace are coupled to each other at first node. One terminal of each of the at least two sub-traces of second trace are coupled to each other at second node. One terminal of third trace is coupled to second trace, and another terminal of third trace is coupled to first input/output terminal. One terminal of fourth trace is coupled to first trace, and another terminal of fourth trace is coupled to second input/output terminal. First capacitor is coupled to first node and second node. Second capacitor is coupled between first node and first input/output terminal, or coupled between first node and second input/output terminal, or coupled between first input/output terminal and second input/output terminal.