Abstract: A motherboard, a storage device and a controller thereof and a booting method are provided. In the present invention, when powered on, an unfetch signal is transmitted to a central processor unit (CPU) by a controller such that an operation of the CPU is suspended. Next, a system firmware in the storage device is loaded by the controller. After the system firmware is loaded, a fetch-done signal is transmitted to the CPU by the controller such that the CPU starts executing a booting procedure.

Abstract: A method for command transmission between systems is introduced. The command transmission between the systems, such as a north bridge chip, a south bridge chip and a central processing unit (CPU), employs the signals transmission specified by a PCI Express bus originally for the communication between system chips or peripheral devices. The signals transmission includes an interrupt or a system management instruction specified by the PCI Express bus, which further defines the specific addresses of a memory packet and a system message packet. In the preferred embodiment, the method thereof comprises the steps of transmitting an INTA command first, then a second system chip upstreams an INTR/system-management command to a first system chip. After that, the first system chip downstreams an EOI/system-management command to the second system chip.

Abstract: A motherboard, a storage device and a controller thereof and a booting method are provided. In the present invention, when powered on, an unfetch signal is transmitted to a central processor unit (CPU) by a controller such that an operation of the CPU is suspended. Next, a system firmware in the storage device is loaded by the controller. After the system firmware is loaded, a fetch-done signal is transmitted to the CPU by the controller such that the CPU starts executing a booting procedure.

Abstract: A method for command transmission between systems is introduced. The command transmission between the systems, such as a north bridge chip, a south bridge chip and a central processing unit (CPU), employs the signals transmission specified by a PCI Express bus originally for the communication between system chips or peripheral devices. The signals transmission includes an interrupt or a system management instruction specified by the PCI Express bus, which further defines the specific addresses of a memory packet and a system message packet. In the preferred embodiment, the method thereof comprises the steps of transmitting an INTA command first, then a second system chip upstreams an INTR/system-management command to a first system chip. After that, the first system chip downstreams an EOI/system-management command to the second system chip.