Abstract: According to one embodiment, a semiconductor memory device includes: a plurality of first conductive layers aligned in a first direction with a space in between; a first plug penetrating the first conductive layers; a second conductive layer below the first conductive layers, the second conductive layer being coupled to a lower end of the first plug; a first transistor below the first conductive layers; a second transistor in a second region between the first transistor and a first region below the second conductive layer, the second transistor having a gate electrically coupled to the first transistor and a drain electrically coupled to the first transistor; and a third transistor in the second region, the third transistor having a source and a drain electrically coupled to each other.