Patents by Inventor You LUO

You LUO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11911870
    Abstract: Embodiments herein generally relate to polishing pads and methods of forming polishing pads. A polishing pad includes a plurality of polishing elements. Each polishing element comprises an individual surface that forms a portion of a polishing surface of the polishing pad and one or more sidewalls extending downwardly from the individual surface to define a plurality of channels disposed between the polishing elements. Each of the polishing elements has a plurality of pore-features formed therein. Each of the polishing elements is formed of a pre-polymer composition and a sacrificial material composition. In some cases, a sample of the cured pre-polymer composition has a glass transition temperature (Tg) of about 80° C. or greater. A storage modulus (E?) of the cured pre-polymer composition at a temperature of 80° C. (E?80) can be about 200 MPa or greater.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: February 27, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Sivapackia Ganapathiappan, Rajeev Bajaj, Yingdong Luo, Aniruddh Jagdish Khanna, You Wang, Daniel Redfield
  • Publication number: 20230369407
    Abstract: The current disclosure describes techniques for individually selecting the number of channel strips for a device. The channel strips are selected by defining a three-dimensional active region that include a surface active area and a depth/height. Semiconductor strips in the active region are selected as channel strips. Semiconductor strips contained in the active region will be configured to be channel strips. Semiconductor strips not included in the active region are not selected as channel strips and are separated from source/drain structures by an auxiliary buffer layer.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Inventors: Ya-Jui Tsou, Zong-You Luo, Wen Hung Huang, Jhih-Yang Yan, Chee-Wee Liu
  • Publication number: 20230363287
    Abstract: A method includes forming a memory stack over a substrate. A dielectric layer is deposited to cover the memory stack. An opening is formed in the dielectric layer. The opening does not expose the memory stack. A spin-orbit-torque (SOT) layer is formed in the opening. A free layer is formed over the dielectric layer to interconnect the memory stack and the SOT layer.
    Type: Application
    Filed: July 17, 2023
    Publication date: November 9, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Ya-Jui TSOU, Zong-You LUO, Chee-Wee LIU, Shao-Yu LIN, Liang-Chor CHUNG, Chih-Lin WANG
  • Publication number: 20230360686
    Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.
    Type: Application
    Filed: July 14, 2023
    Publication date: November 9, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Zong-You LUO, Ya-Jui TSOU, Chee-Wee LIU, Shao-Yu LIN, Liang-Chor CHUNG, Chih-Lin WANG
  • Patent number: 11778923
    Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer, a spacer layer over the pinned layer, a reference layer over the spacer layer, and a tunnel barrier layer over the reference layer. The SOT layer has a top surface substantially coplanar with a top surface of the tunnel barrier layer of the memory stack. The free layer interconnects the SOT layer and the tunnel barrier layer.
    Type: Grant
    Filed: November 14, 2021
    Date of Patent: October 3, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Ya-Jui Tsou, Zong-You Luo, Chee-Wee Liu, Shao-Yu Lin, Liang-Chor Chung, Chih-Lin Wang
  • Patent number: 11749328
    Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: September 5, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Zong-You Luo, Ya-Jui Tsou, Chee-Wee Liu, Shao-Yu Lin, Liang-Chor Chung, Chih-Lin Wang
  • Patent number: 11742388
    Abstract: The current disclosure describes techniques for individually selecting the number of channel strips for a device. The channel strips are selected by defining a three-dimensional active region that include a surface active area and a depth/height. Semiconductor strips in the active region are selected as channel strips. Semiconductor strips contained in the active region will be configured to be channel strips. Semiconductor strips not included in the active region are not selected as channel strips and are separated from source/drain structures by an auxiliary buffer layer.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: August 29, 2023
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan University
    Inventors: Ya-Jui Tsou, Zong-You Luo, Wen Hung Huang, Jhih-Yang Yan, Chee-Wee Liu
  • Patent number: 11605670
    Abstract: The disclosure is directed to spin-orbit torque MRAM structures and methods. A SOT channel of the SOT-MRAM includes multiple heavy metal layers and one or more dielectric dusting layers each sandwiched between two adjacent heavy metal layers. The dielectric dusting layers each include discrete molecules or discrete molecule clusters of a dielectric material scattered in or adjacent to an interface between two adjacent heavy metal layers.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: March 14, 2023
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan University
    Inventors: Zong-You Luo, Ya-Jui Tsou, I-Cheng Tung, CheeWee Liu
  • Publication number: 20230015775
    Abstract: The current disclosure describes techniques for individually selecting the number of channel strips for a device. The channel strips are selected by defining a three-dimensional active region that include a surface active area and a depth/height. Semiconductor strips in the active region are selected as channel strips. Semiconductor strips contained in the active region will be configured to be channel strips. Semiconductor strips not included in the active region are not selected as channel strips and are separated from source/drain structures by an auxiliary buffer layer.
    Type: Application
    Filed: July 22, 2022
    Publication date: January 19, 2023
    Inventors: Ya-Jui Tsou, Zong-You Luo, Wen Hung Huang, Jhih-Yang Yan, Chee-Wee Liu
  • Publication number: 20220359615
    Abstract: The disclosure is directed to spin-orbit torque MRAM structures and methods. A SOT channel of the SOT-MRAM includes multiple heavy metal layers and one or more dielectric dusting layers each sandwiched between two adjacent heavy metal layers. The dielectric dusting layers each include discrete molecules or discrete molecule clusters of a dielectric material scattered in or adjacent to an interface between two adjacent heavy metal layers.
    Type: Application
    Filed: July 22, 2022
    Publication date: November 10, 2022
    Inventors: Zong-You Luo, Ya-Jui Tsou, I-Cheng Tung, CheeWee Liu
  • Publication number: 20220358980
    Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Zong-You LUO, Ya-Jui TSOU, Chee-Wee LIU, Shao-Yu LIN, Liang-Chor CHUNG, Chih-Lin WANG
  • Patent number: 11411082
    Abstract: The current disclosure describes techniques for individually selecting the number of channel strips for a device. The channel strips are selected by defining a three-dimensional active region that include a surface active area and a depth/height. Semiconductor strips in the active region are selected as channel strips. Semiconductor strips contained in the active region will be configured to be channel strips. Semiconductor strips not included in the active region are not selected as channel strips and are separated from source/drain structures by an auxiliary buffer layer.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: August 9, 2022
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan University
    Inventors: Ya-Jui Tsou, Zong-You Luo, Wen Hung Huang, Jhih-Yang Yan, Chee-Wee Liu
  • Patent number: 11410714
    Abstract: A magnetoresistive memory device includes a plurality of bottom conductive lines, a plurality of top conductive lines, a first memory cell, and a second memory cell. The top conductive lines are over the bottom conductive lines. The first memory cell is between the bottom conductive lines and the top conductive lines and includes a first magnetic tunnel junction (MTJ) stack. The second memory cell is adjacent the first memory cell and between the bottom conductive lines and the top conductive lines. The second memory cell includes a second MTJ stack, and a top surface of the second MTJ stack is higher than a top surface of the first MTJ stack.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: August 9, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Zong-You Luo, Ya-Jui Tsou, Chee-Wee Liu, Shao-Yu Lin, Liang-Chor Chung, Chih-Lin Wang
  • Patent number: 11398233
    Abstract: The embodiments of the present disclosure provides a smart service method, apparatus and device, the method includes: a first device plays response information corresponding to an awaking word after receiving the awaking word; when the first device determines that a second device in an awake state exists in a device group that the first device is in, the first device transmits operation information of the first device to the second device, and receives operation information of the second device transmitted by the second device; the first device determines, according to the operation information of the first device and the operation information of the second device a target device from the first device and the second device, where the target device is a device in the device group to provide a smart service. The service resources are economized.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: July 26, 2022
    Assignee: BAIDU ONLINE NETWORK TECHNOLOGY (BEIJING) CO., LTD.
    Inventors: Cong Gao, You Luo
  • Publication number: 20220077384
    Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer, a spacer layer over the pinned layer, a reference layer over the spacer layer, and a tunnel barrier layer over the reference layer. The SOT layer has a top surface substantially coplanar with a top surface of the tunnel barrier layer of the memory stack. The free layer interconnects the SOT layer and the tunnel barrier layer.
    Type: Application
    Filed: November 14, 2021
    Publication date: March 10, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Ya-Jui TSOU, Zong-You LUO, Chee-Wee LIU, Shao-Yu LIN, Liang-Chor CHUNG, Chih-Lin WANG
  • Patent number: 11177430
    Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer and a reference layer over the pinned layer. The SOT layer is spaced apart from the memory stack. The free layer is over the memory stack and the SOT layer.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: November 16, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Ya-Jui Tsou, Zong-You Luo, Chee-Wee Liu, Shao-Yu Lin, Liang-Chor Chung, Chih-Lin Wang
  • Publication number: 20210210091
    Abstract: The disclosure discloses a method, a device, and a storage medium for waking up via a speech. The method includes: collecting a wake-up speech of a user; generating wake-up information of a current intelligent device based on the wake-up speech and state information of the current intelligent device; sending the wake-up information of the current intelligent device to one or more non-current intelligent devices in a network; receiving wake-up information from the one or more non-current intelligent devices in the network; determining whether the current intelligent device is a target speech interaction device in combination with wake-up information of each intelligent device in the network; and controlling the current intelligent device to perform speech interaction with the user in a case that the current intelligent device is the target speech interaction device.
    Type: Application
    Filed: September 14, 2020
    Publication date: July 8, 2021
    Inventors: Xue MI, Rongsheng HUANG, Peng WANG, Yang MENG, You LUO, Xiaolong JIANG, Lu JIN, Xiwang JIANG, Xuan LI
  • Publication number: 20210082482
    Abstract: A magnetoresistive memory device includes a plurality of bottom conductive lines, a plurality of top conductive lines, a first memory cell, and a second memory cell. The top conductive lines are over the bottom conductive lines. The first memory cell is between the bottom conductive lines and the top conductive lines and includes a first magnetic tunnel junction (MTJ) stack. The second memory cell is adjacent the first memory cell and between the bottom conductive lines and the top conductive lines. The second memory cell includes a second MTJ stack, and a top surface of the second MTJ stack is higher than a top surface of the first MTJ stack.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Zong-You LUO, Ya-Jui TSOU, Chee-Wee LIU, Shao-Yu LIN, Liang-Chor CHUNG, Chih-Lin WANG
  • Publication number: 20210043203
    Abstract: The embodiments of the present disclosure provides a smart service method, apparatus and device, the method includes: a first device plays response information corresponding to an awaking word after receiving the awaking word; when the first device determines that a second device in an awake state exists in a device group that the first device is in, the first device transmits operation information of the first device to the second device, and receives operation information of the second device transmitted by the second device; the first device determines, according to the operation information of the first device and the operation information of the second device a target device from the first device and the second device, where the target device is a device in the device group to provide a smart service. The service resources are economized.
    Type: Application
    Filed: April 24, 2020
    Publication date: February 11, 2021
    Applicant: Baidu Online Network Technology (Beijing) Co., Ltd.
    Inventors: Cong GAO, You LUO
  • Publication number: 20200395530
    Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer and a reference layer over the pinned layer. The SOT layer is spaced apart from the memory stack. The free layer is over the memory stack and the SOT layer.
    Type: Application
    Filed: June 17, 2019
    Publication date: December 17, 2020
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Ya-Jui TSOU, Zong-You LUO, Chee-Wee LIU, Shao-Yu LIN, Liang-Chor CHUNG, Chih-Lin WANG