Patents by Inventor Youfeng He
Youfeng He has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10431671Abstract: A method is provided for fabricating fin field-effect transistors. The method includes providing a substrate. The method also includes forming a plurality of fins on a surface of the substrate. Further the method includes forming a transitional layer having atoms identical to atoms of the fins on side and top surfaces of the plurality of fins by a deposition process. Further, the method also includes performing an oxidation process to convert the transitional layer and a surface portion of the fins into a dielectric material to form a gate dielectric layer on the plurality of fins.Type: GrantFiled: December 7, 2017Date of Patent: October 1, 2019Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Xiaopeng Yu, Youfeng He, Zhengling Chen
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Publication number: 20180097090Abstract: A method is provided for fabricating fin field-effect transistors. The method includes providing a substrate. The method also includes forming a plurality of fins on a surface of the substrate. Further the method includes forming a transitional layer having atoms identical to atoms of the fins on side and top surfaces of the plurality of fins by a deposition process. Further, the method also includes performing an oxidation process to convert the transitional layer and a surface portion of the fins into a dielectric material to form a gate dielectric layer on the plurality of fins.Type: ApplicationFiled: December 7, 2017Publication date: April 5, 2018Inventors: XIAOPENG YU, YOUFENG HE, ZHENGLING CHEN
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Patent number: 9871120Abstract: A method is provided for fabricating fin field-effect transistors. The method includes providing a substrate. The method also includes forming a plurality of fins on a surface of the substrate. Further the method includes forming a transitional layer having atoms identical to atoms of the fins on side and top surfaces of the plurality of fins by a deposition process. Further, the method also includes performing an oxidation process to convert the transitional layer and a surface portion of the fins into a dielectric material to form a gate dielectric layer on the plurality of fins.Type: GrantFiled: May 14, 2015Date of Patent: January 16, 2018Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Xiaopeng Yu, Youfeng He, Zhengling Chen
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Publication number: 20150380241Abstract: A method is provided for fabricating fin field-effect transistors. The method includes providing a substrate. The method also includes forming a plurality of fins on a surface of the substrate. Further the method includes forming a transitional layer having atoms identical to atoms of the fins on side and top surfaces of the plurality of fins by a deposition process. Further, the method also includes performing an oxidation process to convert the transitional layer and a surface portion of the fins into a dielectric material to form a gate dielectric layer on the plurality of fins.Type: ApplicationFiled: May 14, 2015Publication date: December 31, 2015Inventors: XIAOPENG YU, YOUFENG HE, ZHENGLING CHEN
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Patent number: 8933428Abstract: The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, a plurality of peripheral shallow trench isolation (STI) units in the peripheral substrate, and at least one MOS transistor on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, a plurality of vertical LEDs on the N-type ion buried layer, a plurality of storage shallow trench isolation (STI) units between the vertical LEDs, and a plurality of phase change layers on the vertical LED and between the storage STI units. The storage STI units have thickness substantially equal to thickness of the vertical LEDs. The peripheral STI units have thickness substantially equal to thickness of the storage STI units. The N-type conductive region contains SiC.Type: GrantFiled: June 5, 2013Date of Patent: January 13, 2015Assignee: Semiconductor Manufacturing International (Beijing) CorporationInventors: Fumitake Mieno, Youfeng He
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Publication number: 20140191301Abstract: Transistors and fabrication methods are provided. A first sidewall can be formed on each sidewall of a gate structure. A second sidewall can be formed on the first sidewall. The first sidewall can be made of a doped material. After forming a source and a drain, a metal silicide layer can be formed on the source and the drain. The second sidewall can be removed to expose a surface portion of the semiconductor substrate between the metal silicide layer and the first silicide layer. A stress layer can be formed on the exposed surface portion of the semiconductor substrate, on the metal silicide layer, on the first sidewall, and on the gate.Type: ApplicationFiled: November 22, 2013Publication date: July 10, 2014Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: YOUFENG HE, YONGGEN HE
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Publication number: 20130320416Abstract: A semiconductor device and a method for forming the same are provided. The method includes: providing a substrate having a gate structure and first spacers on both sidewalls of the gate structure formed on a top surface of the substrate; forming first openings in the substrate by using the first spacers as a mask, wherein the first openings are located on both sides of the gate structure; forming second openings by etching the first openings with an etching gas, wherein each of the second openings is an expansion of a corresponding one of the first openings toward the gate structure and extends to underneath an adjacent first spacer; and forming epitaxial layers in the first openings and the second openings.Type: ApplicationFiled: August 8, 2013Publication date: December 5, 2013Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventor: Youfeng He
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Patent number: 8581311Abstract: A semiconductor device and a method for forming the same are provided. The method includes: providing a substrate having a gate structure and first spacers on both sidewalls of the gate structure formed on a top surface of the substrate; forming first openings in the substrate by using the first spacers as a mask, wherein the first openings are located on both sides of the gate structure; forming second openings by etching the first openings with an etching gas, wherein each of the second openings is an expansion of a corresponding one of the first openings toward the gate structure and extends to underneath an adjacent first spacer; and forming epitaxial layers in the first openings and the second openings.Type: GrantFiled: August 8, 2013Date of Patent: November 12, 2013Assignee: Semiconductor Manufacturing International (Beijing) CorporationInventor: Youfeng He
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Publication number: 20130264537Abstract: The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, a plurality of peripheral shallow trench isolation (STI) units in the peripheral substrate, and at least one MOS transistor on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, a plurality of vertical LEDs on the N-type ion buried layer, a plurality of storage shallow trench isolation (STI) units between the vertical LEDs, and a plurality of phase change layers on the vertical LED and between the storage STI units. The storage STI units have thickness substantially equal to thickness of the vertical LEDs. The peripheral STI units have thickness substantially equal to thickness of the storage STI units. The N-type conductive region contains SiC.Type: ApplicationFiled: June 5, 2013Publication date: October 10, 2013Inventors: Fumitake Mieno, Youfeng He
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Patent number: 8536001Abstract: A method for forming a semiconductor device is provided. The exemplary method includes: providing a substrate having a gate structure and first spacers on both sidewalls of the gate structure formed on a top surface of the substrate; forming first openings in the substrate by using the first spacers as a mask, wherein the first openings are located on both sides of the gate structure; forming second openings by etching the first openings with an etching gas, wherein each of the second openings is an expansion of a corresponding one of the first openings toward the gate structure and extends to underneath an adjacent first spacer; and forming epitaxial layers in the first openings and the second openings.Type: GrantFiled: November 29, 2011Date of Patent: September 17, 2013Assignee: Semiconductor Manufacturing International (Beijing) CorporationInventor: Youfeng He
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Patent number: 8481348Abstract: The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, a plurality of peripheral shallow trench isolation (STI) units in the peripheral substrate, and at least one MOS transistor on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, a plurality of vertical LEDs on the N-type ion buried layer, a plurality of storage shallow trench isolation (STI) units between the vertical LEDs, and a plurality of phase change layers on the vertical LED and between the storage STI units. The storage STI units have thickness substantially equal to thickness of the vertical LEDs. The peripheral STI units have thickness substantially equal to thickness of the storage STI units. The N-type conductive region contains SiC.Type: GrantFiled: July 5, 2011Date of Patent: July 9, 2013Assignee: Semiconductor Manufacturing International Corp.Inventors: Fumitake Mieno, Youfeng He
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Patent number: 8409883Abstract: The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, peripheral shallow trench isolation (STI) units in the peripheral substrate, and MOS transistors on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, vertical LEDs on the on the N-type ion buried layer, storage shallow trench isolation (STI) units between the vertical LEDs, and phase change layers on the vertical LEDs and between the storage STI units. The storage STI units have thickness equal to thickness of the vertical LEDs. Each vertical LED comprises an N-type conductive region on the N-type ion buried layer, and a P-type conductive region on the N-type conductive region. The P-type conductive region contains SiGe.Type: GrantFiled: June 9, 2011Date of Patent: April 2, 2013Assignee: Semiconductor Manufacturing International Corp.Inventors: Fumitake Mieno, Youfeng He
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Publication number: 20120161092Abstract: The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, a plurality of peripheral shallow trench isolation (STI) units in the peripheral substrate, and at least one MOS transistor on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, a plurality of vertical LEDs on the N-type ion buried layer, a plurality of storage shallow trench isolation (STI) units between the vertical LEDs, and a plurality of phase change layers on the vertical LED and between the storage STI units. The storage STI units have thickness substantially equal to thickness of the vertical LEDs. The peripheral STI units have thickness substantially equal to thickness of the storage STI units. The N-type conductive region contains SiC.Type: ApplicationFiled: July 5, 2011Publication date: June 28, 2012Applicant: Semiconductor Manufacturing International (Beijing) CorporationInventors: Fumitake Mieno, Youfeng He
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Publication number: 20120161097Abstract: The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, peripheral shallow trench isolation (STI) units in the peripheral substrate, and MOS transistors on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, vertical LEDs on the on the N-type ion buried layer, storage shallow trench isolation (STI) units between the vertical LEDs, and phase change layers on the vertical LEDs and between the storage STI units. The storage STI units have thickness equal to thickness of the vertical LEDs. Each vertical LED comprises an N-type conductive region on the N-type ion buried layer, and a P-type conductive region on the N-type conductive region. The P-type conductive region contains SiGe.Type: ApplicationFiled: June 9, 2011Publication date: June 28, 2012Applicant: Semiconductor Manufacturing International (Beijing) CorporationInventors: Fumitake MIENO, Youfeng HE
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Publication number: 20120139016Abstract: A semiconductor device and a method for forming the same are provided. The method includes: providing a substrate having a gate structure and first spacers on both sidewalls of the gate structure formed on a top surface of the substrate; forming first openings in the substrate by using the first spacers as a mask, wherein the first openings are located on both sides of the gate structure; forming second openings by etching the first openings with an etching gas, wherein each of the second openings is an expansion of a corresponding one of the first openings toward the gate structure and extends to underneath an adjacent first spacer; and forming epitaxial layers in the first openings and the second openings.Type: ApplicationFiled: November 29, 2011Publication date: June 7, 2012Applicant: Semiconductor Manufacturing International (Beijing) CorporationInventor: Youfeng He