Patents by Inventor Youhei Fukazawa
Youhei Fukazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11431995Abstract: According to one embodiment, a memory system includes a frequency value update unit, a first intra-group rearranging unit, a second intra-group rearranging unit, and a routing unit. The frequency value update unit adds a first value to each of one or more first frequency values that are associated with one or more first symbols, respectively, in one or more entries in a table. The first intra-group rearranging unit rearranges first entries, which belong to a first group, using frequency values in the first entries. The second intra-group rearranging unit rearranges second entries, which belong to a second group lower than the first group, using frequency values. The routing unit rearranges at least one of the first entries and at least one of the second entries.Type: GrantFiled: September 14, 2020Date of Patent: August 30, 2022Assignee: Kioxia CorporationInventors: Daisuke Yashima, Masato Sumiyoshi, Keiri Nakanishi, Takashi Miura, Kohei Oikawa, Sho Kodama, Youhei Fukazawa, Zheye Wang
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Publication number: 20220269416Abstract: According to one embodiment, a memory system includes a compressor configured to output second data obtained by compressing input first data and a non-volatile memory to which third data based on the second data output from the compressor is written. The compressor includes a dictionary coding unit configured to perform dictionary coding on the first data, an entropy coding unit configured to perform entropy coding on the result of the dictionary coding, a first calculation unit configured to calculate compression efficiencies of the dictionary coding and the entropy coding, and a first control unit configured to control an operation of at least one of the dictionary coding unit and the entropy coding unit based on the compression efficiencies and a power reduction level.Type: ApplicationFiled: June 14, 2021Publication date: August 25, 2022Applicant: Kioxia CorporationInventors: Sho KODAMA, Keiri NAKANISHI, Masato SUMIYOSHI, Zheye WANG, Kohei OIKAWA, Youhei FUKAZAWA, Daisuke YASHIMA, Takashi MIURA
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Publication number: 20220255556Abstract: According to one embodiment, a buffer stores first hash values and first complementary data. A first conversion unit converts consecutive characters in a second character string into second hash values and second complementary data. A search unit searches for consecutive first hash values from the buffer, and output a pointer. A selection unit selects consecutive first hash values and pieces of first complementary data from the buffer. A second conversion unit converts the consecutive first hash values into a third character string using the pieces of first complementary data. A comparison unit compares the second character string with the third character string to acquire a matching length. An output unit output the matching length with the pointer.Type: ApplicationFiled: September 10, 2021Publication date: August 11, 2022Inventors: Daisuke YASHIMA, Kohei OIKAWA, Sho KODAMA, Keiri NAKANISHI, Masato SUMIYOSHI, Youhei FUKAZAWA, Zheye WANG, Takashi MIURA
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Patent number: 11397546Abstract: A memory system including a storage device and a memory controller controlling the storage device and decoding an encoded data. The memory controller including: a history buffer storing a decoded data string; a history buffer read controller executing a read request to the history buffer; a decode executing section generating a first shaped data string based on the decoded data string read from the history buffer, generating a second shaped data string by referring the first shaped data string before the first shaped data string being written back to the history buffer in response to the read request, and generating a decoded result using the first shaped data string and the second shaped data string.Type: GrantFiled: July 29, 2020Date of Patent: July 26, 2022Assignee: Kioxia CorporationInventors: Masato Sumiyoshi, Keiri Nakanishi, Takashi Miura, Kohei Oikawa, Daisuke Yashima, Sho Kodama, Youhei Fukazawa, Zheye Wang
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Publication number: 20220187994Abstract: According to one embodiment, a compression device includes a first storage unit, a second storage unit, a calculation unit, and a comparison unit. The first storage unit stores addresses associated with hash values, respectively. The second storage unit includes storage areas specified by the addresses, respectively. The calculation unit determines a hash function to be used for first data in accordance with at least a part of the first data, and calculates a hash value using the hash function and at least a part of second data included in the first data. The comparison unit acquires third data from a storage area in the second storage unit specified by a first address, and compares the second data with the third data. The first address is stored in the first storage unit and is associated with the hash value.Type: ApplicationFiled: September 9, 2021Publication date: June 16, 2022Inventors: Youhei FUKAZAWA, Kohei OIKAWA, Sho KODAMA, Keiri NAKANISHI, Takashi MIURA, Daisuke YASHIMA, Masato SUMIYOSHI, Zheye WANG
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Publication number: 20220171724Abstract: According to one embodiment, a memory system includes a first compression unit, a second compression unit, a non-volatile memory, a first decoding unit, a conversion unit and an output unit. The first compression unit is configured to output second data obtained by compressing first data. The second compression unit is configured to output third data obtained by compressing the second data. Fourth data based on the third data is written to the non-volatile memory. The first decoding unit is configured to decode the third data based on the fourth data to the second data. The conversion unit is configured to acquire fifth data by converting a format of the second data. The output unit is configured to output the fifth data to a host.Type: ApplicationFiled: June 11, 2021Publication date: June 2, 2022Applicant: Kioxia CorporationInventors: Keiri NAKANISHI, Kazuhiro HIWADA, Youhei FUKAZAWA
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Patent number: 11309909Abstract: A compression device includes a dictionary based encoder, a second buffer, a comparator, and a compression data generator. The dictionary based encoder searches for second data at least partially matching first data from a first buffer, and acquires a first match position indicating a position of the second data in the first buffer and a match length indicating a matched length of the first and second data. The second buffer stores the previously acquired second match position with an index. The compression data generator generates first compressed data that includes the index assigned to the second match position in the second buffer and the match length when the first match position matches the second match position in the second buffer.Type: GrantFiled: September 2, 2020Date of Patent: April 19, 2022Assignee: Kioxia CorporationInventors: Youhei Fukazawa, Keiri Nakanishi, Sho Kodama, Masato Sumiyoshi, Kohei Oikawa, Daisuke Yashima, Takashi Miura, Zheye Wang
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Patent number: 11218163Abstract: A memory system includes a nonvolatile memory, an interface circuit, and a controller configured to upon receipt of a plurality of write commands for storing write data in the nonvolatile memory via the interface circuit, acquire compression-ratio information about the write data associated with each write command, determine a compression ratio of each write data based on the acquired compression-ratio information, and determine an execution order of the write commands based on the determined compression ratio.Type: GrantFiled: September 30, 2020Date of Patent: January 4, 2022Assignee: TOSHIBA MEMORY CORPORATIONInventors: Keiri Nakanishi, Youhei Fukazawa
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Publication number: 20210294500Abstract: A memory system including a history buffer, a hash calculator, a read pointer table, a history buffer writing circuit, a read pointer writing circuit, a read pointer reading circuit, a history buffer reading circuit, a matching circuit replacing the input data string with a reference information referring the matching candidate data string in the case where at least a part of the input data string and a part of the matching candidate data string match. Reading of the read pointer by the read pointer reading circuit and reading of the stored input data string by the history buffer reading circuit are executed after writing of the read pointer by the read pointer writing circuit and writing of the input data string by the history buffer writing circuit are finished.Type: ApplicationFiled: August 20, 2020Publication date: September 23, 2021Applicant: Kioxia CorporationInventors: Sho KODAMA, Keiri Nakanishi, Kohei Oikawa, Daisuke Yashima, Masato Sumiyoshi, Youhei Fukazawa
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Publication number: 20210294525Abstract: A memory system including a storage device and a memory controller controlling the storage device and decoding an encoded data. The memory controller including: a history buffer storing a decoded data string; a history buffer read controller executing a read request to the history buffer; a decode executing section generating a first shaped data string based on the decoded data string read from the history buffer, generating a second shaped data string by refferring the first shaped data string before the first shaped data string being written back to the history buffer in response to the read request, and generating a decoded result using the first shaped data string and the second shaped data string.Type: ApplicationFiled: July 29, 2020Publication date: September 23, 2021Applicant: Kioxia CorporationInventors: Masato Sumiyoshi, Keiri Nakanishi, Takashi Miura, Kohei Oikawa, Daisuke Yashima, Sho Kodama, Youhei Fukazawa, Zheye Wang
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Publication number: 20210289217Abstract: According to one embodiment, a memory system includes a frequency value update unit, a first intra-group rearranging unit, a second intra-group rearranging unit, and a routing unit. The frequency value update unit adds a first value to each of one or more first frequency values that are associated with one or more first symbols, respectively, in one or more entries in a table. The first intra-group rearranging unit rearranges first entries, which belong to a first group, using frequency values in the first entries. The second intra-group rearranging unit rearranges second entries, which belong to a second group lower than the first group, using frequency values. The routing unit rearranges at least one of the first entries and at least one of the second entries.Type: ApplicationFiled: September 14, 2020Publication date: September 16, 2021Applicant: Kioxia CorporationInventors: Daisuke YASHIMA, Masato SUMIYOSHI, Keiri NAKANISHI, Takashi MIURA, Kohei OIKAWA, Sho KODAMA, Youhei FUKAZAWA, Zheye WANG
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Publication number: 20210288662Abstract: According to one embodiment, a compression device includes a dictionary based encoder, a second buffer, a comparator, and a compression data generator. The dictionary based encoder searches for second data at least partially matching first data from a first buffer, and acquires a first match position indicating a position of the second data in the first buffer and a match length indicating a matched length of the first and second data. The second buffer stores the previously acquired second match position with an index. The compression data generator generates first compressed data that includes the index assigned to the second match position in the second buffer and the match length when the first match position matches the second match position in the second buffer.Type: ApplicationFiled: September 2, 2020Publication date: September 16, 2021Applicant: Kioxia CorporationInventors: Youhei FUKAZAWA, Keiri NAKANISHI, Sho KODAMA, Masato SUMIYOSHI, Kohei OIKAWA, Daisuke YASHIMA, Takashi MIURA, Zheye WANG
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Publication number: 20210021280Abstract: A memory system includes a nonvolatile memory, an interface circuit, and a controller configured to upon receipt of a plurality of write commands for storing write data in the nonvolatile memory via the interface circuit, acquire compression-ratio information about the write data associated with each write command, determine a compression ratio of each write data based on the acquired compression-ratio information, and determine an execution order of the write commands based on the determined compression ratio.Type: ApplicationFiled: September 30, 2020Publication date: January 21, 2021Inventors: Keiri NAKANISHI, Youhei FUKAZAWA
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Patent number: 10826526Abstract: A memory system includes a nonvolatile memory, an interface circuit, and a controller configured to upon receipt of a plurality of write commands for storing write data in the nonvolatile memory via the interface circuit, acquire compression-ratio information about the write data associated with each write command, determine a compression ratio of each write data based on the acquired compression-ratio information, and determine an execution order of the write commands based on the determined compression ratio.Type: GrantFiled: August 23, 2019Date of Patent: November 3, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Keiri Nakanishi, Youhei Fukazawa
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Publication number: 20200304142Abstract: A memory system includes a nonvolatile memory, an interface circuit, and a controller configured to upon receipt of a plurality of write commands for storing write data in the nonvolatile memory via the interface circuit, acquire compression-ratio information about the write data associated with each write command, determine a compression ratio of each write data based on the acquired compression-ratio information, and determine an execution order of the write commands based on the determined compression ratio.Type: ApplicationFiled: August 23, 2019Publication date: September 24, 2020Inventors: Keiri NAKANISHI, Youhei FUKAZAWA
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Patent number: 10489243Abstract: According to one embodiment, for first data, which is read from a nonvolatile memory, for which a first data translation is performed, a second data translation that is a reverse translation of the first data translation is performed. Next, for the first data for which the second data translation is performed, the first data translation is performed. In addition, the read first data is compared with the first data for which the first data translation is performed, and check information is generated based on a result of the comparison.Type: GrantFiled: September 15, 2017Date of Patent: November 26, 2019Assignee: Toshiba Memory CorporationInventors: Kazuki Inoue, Sho Kodama, Keiri Nakanishi, Kohei Oikawa, Youhei Fukazawa
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Patent number: 10193579Abstract: According to an embodiment, a storage control device includes a controller, a compression condition determiner, a compressor, and an error correction encoder. The controller receives a write request for a data item and determines whether or not the wear degree of a target region in a storage device to which the data item is to be written is less than a threshold value. The compression condition determiner determines, based on the wear degree, an optimal compression condition out of compression conditions that include lossy compression. The compressor generates, based on the compression condition, compressed data. The error correction encoder subjects the data item to error correction and generates encoded data.Type: GrantFiled: September 7, 2016Date of Patent: January 29, 2019Assignee: Toshiba Memory CorporationInventors: Keiri Nakanishi, Katsuyuki Nomura, Sho Kodama, Youhei Fukazawa, Kazuki Inoue, Kojiro Suzuki, Harutaka Goto
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Publication number: 20180260274Abstract: According to one embodiment, for first data, which is read from a nonvolatile memory, for which a first data translation is performed, a second data translation that is a reverse translation of the first data translation is performed. Next, for the first data for which the second data translation is performed, the first data translation is performed. In addition, the read first data is compared with the first data for which the first data translation is performed, and check information is generated based on a result of the comparison.Type: ApplicationFiled: September 15, 2017Publication date: September 13, 2018Inventors: Kazuki Inoue, Sho Kodama, Keiri Nakanishi, Kohei Oikawa, Youhei Fukazawa
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Patent number: 9792884Abstract: According to one embodiment, an image processing apparatus includes an encoding unit that compresses an input image for each pixel block having a size smaller than a line to generate a plurality of compressed blocks, and store the compressed blocks in a frame buffer, a reading unit that identifies an object block to be expanded among the compressed blocks, and reads the object block from the frame buffer, a decoding unit that expands the object block to generate an expanded block, and an information acquiring unit that acquires, based on the expanded block, position information used by the reading unit to identify the block to be expanded, or decode information used by the decoding unit to expand another compressed block.Type: GrantFiled: January 5, 2016Date of Patent: October 17, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Youhei Fukazawa, Keiri Nakanishi, Masashi Jobashi, Sho Kodama
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Publication number: 20170070244Abstract: According to an embodiment, a storage control device includes a controller, a compression condition determiner, a compressor, and an error correction encoder. The controller receives a write request for a data item and determines whether or not the wear degree of a target region in a storage device to which the data item is to be written is less than a threshold value. The compression condition determiner determines, based on the wear degree, an optimal compression condition out of compression conditions that include lossy compression. The compressor generates, based on the compression condition, compressed data. The error correction encoder subjects the data item to error correction and generates encoded data.Type: ApplicationFiled: September 7, 2016Publication date: March 9, 2017Inventors: Keiri Nakanishi, Katsuyuki Nomura, Sho Kodama, Youhei Fukazawa, Kazuki Inoue, Kojiro Suzuki, Harutaka Goto