Abstract: A method for preparing glycolic acid through hydrolysis of alkoxyacetate is provided. The method includes: subjecting raw materials including the alkoxyacetate and water to a reaction in the presence of an acidic molecular sieve catalyst to produce the glycolic acid, where the alkoxyacetate is at least one selected from the group consisting of compounds with a structural formula shown in formula I; and in formula I, R1 and R2 each are independently any one selected from the group consisting of C1-C5 alkyl groups. The glycolic acid production method in the present application can be implemented by a traditional fixed-bed reactor under an atmospheric pressure, which is very suitable for continuous production.

Abstract: A method for preparing glycolic acid and methyl glycolate through hydrolysis of methyl methoxyacetate and methoxyacetic acid is provided. The method includes allowing raw materials including methyl methoxyacetate, methoxyacetic acid, and water to contact and react with a catalyst to produce glycolic acid and methyl glycolate, where the catalyst is at least one selected from the group consisting of a solid acid catalyst, a liquid acid catalyst, a solid base catalyst, and a liquid base catalyst. The method for preparing glycolic acid and methyl glycolate in the present application can be implemented by a traditional fixed-bed reactor, tank reactor, or catalytic distillation reactor under an atmospheric pressure, which is very suitable for continuous production.

Abstract: An automated checkout system modifies received images of machine-readable labels to improve the performance of a label detection model that the system uses to decode item identifiers encoded in the machine-readable labels. For example, the automated checkout system may transform subregions of an image of a machine-readable label to adjust for distortions in the image's depiction of the machine-readable label. Similarly, the automated checkout system may identify readable regions within received images of machine-readable labels and apply a label detection model to those readable regions. By modifying received images of machine-readable labels, these techniques improve on existing computer-vision technologies by allowing for the effective decoding of machine-readable labels based on real-world images using relatively clean training data.

Abstract: A method for manufacturing a fin transistor structure includes the following: a substrate is provided, a fin part protruding from a top surface of the substrate; an isolation layer is formed on the substrate, a top surface of the isolation layer being lower than a top of the fin part, so that an upper part of the fin part is exposed above the isolation layer; and doping processing is performed on the upper part of the fin part by a diffusion process to form at least one of a source region or a drain region in the upper part of the fin part.

Abstract: A semiconductor device, including: a substrate; an active pillar array structure located on the substrate; and a plurality of first word lines and a plurality of second word lines. The active pillar array structure includes a plurality of active pillars arrayed in a second direction and a third direction, each active pillar extends in a first direction. The active pillar includes a first semiconductor layer, a second semiconductor layer and a third semiconductor layer stacked sequentially in the second direction. The first word lines and the second word lines extend in the third direction. Each active pillar arranged in the third direction corresponds to a respective first word line and a respective second word line. Each first word line covers the first semiconductor layer in the respective active pillar, and each second word line covers the third semiconductor layer in the respective active pillar.

Abstract: Embodiments relates to a semiconductor structure and a method for fabricating the same. The method includes: providing a substrate, where an isolation trench is formed in the substrate; forming a first isolation layer in the isolation trench, where the first isolation layer fills the isolation trench, and a crack extending to an upper surface of the first isolation layer along a vertical direction is formed in the first isolation layer; removing part of the first isolation layer by etching back to form an isolation filling groove in communication with a top opening of the crack; and forming a second isolation layer in the isolation filling groove to plug the top opening of the crack, where the first isolation layer and the second isolation layer jointly constitute an isolation structure.

Abstract: A method for manufacturing a semiconductor structure includes the following operations. A structure to be etched is provided. An etched hole is formed in the structure to be etched. Multiple conducting material layer deposition processes are performed until the conducting material layer fills up the etched hole without a void. The method further includes annealing the deposited conducting material layer after at least some of the conducting material layer deposition processes.

Abstract: A method for forming a semiconductor structure includes the following operations. A substrate is provided. The substrate includes double heterostructures arrayed along a first direction and a second direction. Each of the double heterostructures includes a first semiconductor layer, a second semiconductor layer and another first semiconductor layer sequentially arranged along the first direction. A forbidden band gap of the first semiconductor layer is different from a forbidden band gap of the second semiconductor layer. The first direction is perpendicular to the second direction, and both the first direction and the second direction are parallel to a direction of a plane where the substrate is located. A double gate structure is formed on sidewalls of each of the double heterostructures along the first direction.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base; forming a plurality of first trenches arranged in parallel at intervals and extending along a first direction, and an initial active region between two adjacent ones of the first trenches, wherein the initial active region includes a first initial source-drain region close to a bottom of the first trench, a second initial source-drain region away from the bottom of the first trench, and an initial channel region located between the first initial source-drain region and the second initial source-drain region; forming a protective dielectric layer, wherein the protective dielectric layer covers a sidewall of the second initial source-drain region and a sidewall of the initial channel region; thinning the first initial source-drain region.

Abstract: Embodiments relate to a three-dimensional semiconductor structure and a formation method thereof. The three-dimensional semiconductor structure includes: a substrate; and a device structure positioned on a top surface of the substrate. The device structure includes memory rows arranged at intervals along a first direction, each of the memory rows includes memory cells arranged at intervals along a second direction and a gap between adjacent two of the memory cells, and each of the memory cells includes a first stacked layer and a word line structure. The word line structure includes a first part positioned in the first stacked layer and a second part extending out of the first stacked layer along the first direction. At least adjacent two of the memory rows exist, and the second part of the memory cell in one of the memory rows extends into the gap in another one of the memory rows.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base, including a semiconductor substrate, the semiconductor substrate is provided with first trenches extending along a first direction and second trenches extending along a second direction, the first trenches intersect with the second trenches to form a plurality of semiconductor pillars on the semiconductor substrate, the second trench is filled with a first dielectric layer, a second dielectric layer is provided on a top of the semiconductor pillar, and a third dielectric layer is provided on a sidewall of the first trench; an isolation layer, located in the semiconductor substrate below the first trenches and extending along the second direction; and a bit line, located on a surface of the isolation layer and extending along the second direction, the bit line is connected to a bottom of the semiconductor pillar.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor structure includes: a substrate, a first stacked structure is disposed on the substrate, and includes a memory cell array; a plurality of word lines (WLs), arranged at intervals and extending along a first direction; a plurality of bit lines (BLs), arranged at intervals and extending along a second direction, one end of each of the plurality of BLs away from the memory cell array forms a step in the first direction, each BL is provided with a groove on a surface of the step, and the second direction and the first direction cross each other; and a plurality of BL plugs, arranged at intervals and extending along the first direction, one end of each BL plug is correspondingly disposed in the groove of one of the BLs.

Abstract: The present disclosure provides a transistor and a manufacturing method thereof, and a memory, relates to the technical field of semiconductors. The transistor includes: a channel, wherein an accommodation space is formed therein; a gate, provided with a first end and a second end that are opposite, wherein the first end of the gate is located inside the accommodation space, and the second end of the gate is located outside the accommodation space; a dielectric layer, located between the gate and a channel, insulating and isolating the gate and the channel; a source, provided at one end of the channel; and a drain, provided at the other end of the channel, wherein the drain and the source are arranged at intervals along a length direction of the channel, and the source, the drain, and the channel are each made of a semiconductor material.

Abstract: The present disclosure provides a transistor and a manufacturing method thereof, and a memory, and relates to the technical field of semiconductors. The transistor includes: a channel, wherein a plurality of accommodation spaces are formed therein; a plurality of gates, wherein the plurality of gates have a same extension direction and each have a first end and a second end that are opposite, the first end of the gate is located inside one of the accommodation spaces, and the second end of the gate is located outside the corresponding accommodation space; a dielectric layer, located between the gate and the channel, insulating and isolating the gate and the channel; a source, provided at one end of the channel; and a drain, provided at the other end of the channel, wherein the drain and the source are spaced apart.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a switching transistor and a storage transistor. The switching transistor includes a first gate electrode, a first channel layer coating a portion of the first gate electrode, and a first source-drain electrode and a second source-drain electrode both covering a surface of the first channel layer. The storage transistor includes a second gate electrode, a second channel layer coating a portion of the second gate electrode, and a third source-drain electrode and a fourth source-drain electrode both covering a surface of the second channel layer. A portion of the second gate electrode extending out of the second channel layer in a first direction is electrically connected to the second source-drain electrode. The storage transistor is configured to store charge.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors, including: a substrate, a first stacked structure is disposed on the substrate, and the first stacked structure includes a memory cell array; a plurality of word lines (WLs), where the WL is disposed in the first stacked structure and is electrically connected to the memory cell array; a plurality of bit lines (BLs), the BL is disposed beside the first stacked structure, and is electrically connected to the memory cell array; and one end of each BL away from the memory cell array forms a step, and the BL includes a first core layer and a first conductive layer covering the first core layer; and a plurality of BL plugs, each BL plug is in corresponding contact with the first conductive layer of one of the BLs.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a memory cell array, located on the substrate, the memory cell array includes a plurality of transistor units, each of the transistor units includes a first transistor and a second transistor extending along a first direction and electrically connected to each other, and the first direction is parallel to the substrate; a first bit line, penetrating the memory cell array and electrically connected to the first transistor; a second bit line, penetrating the memory cell array and electrically connected to the second transistor; a first word line, electrically connected to the first transistor; and a second word line, electrically connected to the second transistor.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The manufacturing method includes: forming a first insulating layer on a substrate, a plurality of active pillars are arranged at intervals along a first direction and a second direction in the first insulating layer; partially removing the first insulating layer, to form a plurality of first trenches, each first trench exposes the substrate, and is located between two adjacent columns of active pillars; forming an isolation layer in each first trench; removing at least a part of the first insulating layer between adjacent isolation layers, to form a first filling space, the first filling space exposes a peripheral surface of a middle region of the active pillar; and forming a gate structure on the exposed peripheral surface of the active pillar, the gate structures are integrated along the second direction.

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate; and forming a plurality of columns of stacked structures arranged at intervals in a first direction on the substrate, each stacked structures including a plurality of first sacrificial layers and a plurality of active layers that are stacked alternately. Part of each of the first sacrificial layers is removed to form a first trench and a second trench, and part of each of the active layers is exposed from the first trench and the second trench. Next, the exposed active layers are doped by ion doping to form first doped areas and second doped areas.

Abstract: A semiconductor structure includes a substrate and multiple word lines located on a top surface of the substrate. Each of the word lines extends in a direction parallel to the top surface of the substrate. The multiple word lines are arranged at intervals in a direction perpendicular to the top surface of the substrate. Any two adjacent word lines are at least partially staggered with respect to one another in the direction perpendicular to the top surface of the substrate.