Patents by Inventor Younan Hua

Younan Hua has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8207052
    Abstract: There is provided a method of fabrication an integrated circuit comprising providing a substrate with a bond pad formed thereover, the bond pad having a top surface for the formation of bonding connections. A passivation layer is provided over the bond pad followed by an overlying masking layer. The passivation layer is subsequently etched in accordance with the masking layer to form a patterned passivation layer with an opening that exposes a portion of the top surface of the bond pad. After etching the passivation layer, the mask layer is removed by a plasma resist strip followed by a wet solvent clean that removes etch residue from the passivation layer etch. Finally, a bond pad protective layer is grown over the surface of the bond pad. The bond pad may be composed of aluminum and the bond pad protective layer may be aluminum oxide.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: June 26, 2012
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Younan Hua, Shailesh Redkar
  • Patent number: 8061224
    Abstract: Embodiments of the invention provide a method of determining a storage lifetime of a wafer in a storage environment, the storage environment corresponding to an environment having a first value of temperature and a first value of relative humidity, the wafer having a pre-test value of a first contamination parameter, including the steps of: subjecting the wafer to a test environment for a test period, the test environment includes an environment having a second value of temperature and a second value of relative humidity; subsequently, inspecting the wafer thereby to determine a post-test value of a second contamination parameter, wherein the second value of relative humidity is greater than 30% and the second value of wafer temperature is greater than 30° C.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: November 22, 2011
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Siping Zhao, Younan Hua, Ramesh Rao Nistala, Kun Li
  • Publication number: 20100184285
    Abstract: There is provided a method of fabrication an integrated circuit comprising providing a substrate with a bond pad formed thereover, the bond pad having a top surface for the formation of bonding connections. A passivation layer is provided over the bond pad followed by an overlying masking layer. The passivation layer is subsequently etched in accordance with the masking layer to form a patterned passivation layer with an opening that exposes a portion of the top surface of the bond pad. After etching the passivation layer, the mask layer is removed by a plasma resist strip followed by a wet solvent clean that removes etch residue from the passivation layer etch. Finally, a bond pad protective layer is grown over the surface of the bond pad. The bond pad may be composed of aluminum and the bond pad protective layer may be aluminum oxide.
    Type: Application
    Filed: January 16, 2009
    Publication date: July 22, 2010
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Younan HUA, Shailesh REDKAR
  • Publication number: 20090277287
    Abstract: Embodiments of the invention provide a method of determining a storage lifetime of a wafer in a storage environment, the storage environment corresponding to an environment having a first value of temperature and a first value of relative humidity, the wafer having a pre-test value of a first contamination parameter, including the steps of: subjecting the wafer to a test environment for a test period, the test environment includes an environment having a second value of temperature and a second value of relative humidity; subsequently, inspecting the wafer thereby to determine a post-test value of a second contamination parameter, wherein the second value of relative humidity is greater than 30% and the second value of wafer temperature is greater than 30° C.
    Type: Application
    Filed: May 6, 2008
    Publication date: November 12, 2009
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Siping ZHAO, Younan HUA, Ramesh Rao NISTALA, Kun LI