Abstract: A semiconductor memory device having a redundancy circuit, includes a normal memory cell array unit, a redundancy memory cell array unit for recovering defective cells of the normal memory cell array unit, and a memory driving unit for operating the normal memory cell adjacent to the redundancy memory cell array unit immediately after a word line move time ‘tcycle’ is elasped by using address data.

Abstract: A refresh control circuit is provided that includes a control signal latency setting circuit that sets a control signal (CAS) latency, and a refresh mode setting that receives an output signal (REF) from the auto refresh mode decoder and an output signal (SREF) from the self-refresh mode decoder and outputs an output signal.

Abstract: An input/output voltage detection type substrate voltage generation circuit that of effectively prevents the electric potential of the substrate from being increased by varying the driving capability of a substrate voltage generation circuit. The input/output voltage detection type substrate voltage generation circuit preferably varies the driving capability by detecting an input electric potential of a data input/output terminal. The circuit includes a variable period type oscillator for receiving first, second and third signals as inputs to varying periods of the oscillator and a charge pump for pumping an electric charge to the substrate in accordance with a driving signal output from the variable period type oscillator and based on the variable period of the oscillator.