Abstract: A nonvolatile memory device includes a variable resistance memory element and a read circuit coupled to the variable resistance memory element at a first signal node and configured to provide a read current to the variable resistance memory element via the first signal node, to a provide a mirror current at a second signal node responsive to the cell current and to generate an output signal indicative of a state of the variable resistance memory element responsive to a voltage at the second signal node.

Abstract: A sensing circuit includes a plurality of cell read current generators, a reference current generator and a plurality of sense amplifiers. Each of the cell read current generators generates a cell read current from each of a plurality of memory cells. The reference current generator sums the cell read currents to generate a sum current. Each of the sense amplifiers determines data state stored in each of the memory cells based on each of the cell read currents and an average current. The average current is obtained based on the sum current.

Abstract: A bit-line sense amplifier includes a latching unit and a control unit. The latching unit has a plurality of field effect transistors coupled between first and second bit lines. The control unit controls application of a bias voltage to a set of the field effect transistors such that respective pre-charge voltages are generated at the first and second bit lines with drain currents flowing in the field effect transistors during a pre-charge time period, without a bit line bias voltage and with a minimized number of transistors.

Abstract: A current supply circuit comprises a reference voltage generator generating a reference voltage that varies with temperature, a current circuit generating a constant reference current irrespective of the temperature based on the reference voltage, and a current source generating a mirror current by mirroring a base current as a replica current of the reference current.

Abstract: A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits.

Abstract: A circuit for generating a write signal includes a pre-emphasis signal generator that receives location information of a to-be-programmed memory cell and generates a pre-emphasis signal depending on the location information of the to-be-programmed memory cell, and a write driver that generates a program signal corresponding to data to be programmed in the to-be-programmed memory cell. A write signal is generated by combining the program signal with the pre-emphasis signal supplied from the pre-emphasis signal generator, and the write signal output to the to-be-programmed memory cell.

Abstract: A stacked semiconductor device and a method of forming a serial path of the stacked semiconductor device are provided. The stacked semiconductor device includes a plurality of chips each having a first internal circuit for receiving an input signal, performing a designated operation and outputting an output signal. Each of the chips includes a serial bump disposed at the same position on one surface of each of the chips, receiving the input signal and transferring the input signal to the first internal circuit, and a serial through-silicon via (TSV) disposed at a position symmetrical to the serial bump with respect to a center of the chip to penetrate the chip, and receiving and transferring the output signal. Here, the chips are alternately rotated and stacked, so that the serial TSV and the serial bumps of adjacent chips contact each other.

Abstract: The present invention relates to a cooling apparatus for an electronic device. In the present invention, a coolant passing through a condenser 10 is introduced into and s filled in a compensator 15. The coolant passing through the compensator 15 is introduced into a vaporizer 20 and vaporized through heat exchange with an auxiliary heat source H2 provided outside of the vaporizer. In addition, a vaporizing unit 22 made of a porous material is provided in the vaporizer 20. The coolant passing through the vaporizer 20 and a liquid coolant supplied from the condenser 10 are mixed in a vortex generating unit 30 to form a coolant spray, and the coolant spray moves along a spiral trajectory to be formed into a vortex. Meanwhile, the coolant spray of a vortex is injected to be in close contact with the inner wall of an evaporator 50 to be heat-exchanged with a main heat source H1 positioned outside of the evaporator, thereby cooling the main heat source H1.

Abstract: A nonvolatile memory device includes a variable resistance memory element and a read circuit coupled to the variable resistance memory element at a first signal node and configured to provide a read current to the variable resistance memory element via the first signal node, to a provide a mirror current at a second signal node responsive to the cell current and to generate an output signal indicative of a state of the variable resistance memory element responsive to a voltage at the second signal node.

Abstract: A semiconductor device includes; a first pad that receives an external voltage during a test, a second pad coupled to an external impedance during the test, a voltage-current converter coupled to the first pad and the second pad and generating a bias current substantially in response to only the external voltage and the external impedance, and an internal circuit responsive to a test current during the test, such that the level of the test current is defined by the level of the bias current.

Abstract: In a multilayered ceramic capacitor, the width of an exposed portion of an internal electrode is reduced to be narrower than that of a non-exposed portion thereof. A dummy electrode that is not electrically connected to the internal electrode is formed to be connected to an external electrode. Deterioration of reliability due to penetration of the plating solution thereby is prevented and reduction in adhesion of the external electrode due to reduction in width of the exposed portion of the internal electrode is supplemented through mechanical connection between the external electrode and the dummy electrode.

Abstract: A bit-line sense amplifier includes a latching unit and a control unit. The latching unit has a plurality of field effect transistors coupled between first and second bit lines. The control unit controls application of a bias voltage to a set of the field effect transistors such that respective pre-charge voltages are generated at the first and second bit lines with drain currents flowing in the field effect transistors during a pre-charge time period, without a bit line bias voltage and with a minimized number of transistors.

Abstract: A semiconductor device is disclosed including a through electrode. The semiconductor device may include a first semiconductor chip including a transceiver circuit formed on a first surface, a first coupling conductive pattern which is formed on a second surface opposite the first surface, and a through electrode which connects the transceiver circuit and the first coupling conductive pattern. There may be a transceiver located on a second semiconductor chip and including a second coupling conductive pattern facing the first coupling conductive pattern which communicates wirelessly with the first coupling conductive pattern.

Abstract: A bit-line sense amplifier includes a latching unit and a control unit. The latching unit has a plurality of field effect transistors coupled between first and second bit lines. The control unit controls application of a bias voltage to a set of the field effect transistors such that respective pre-charge voltages are generated at the first and second bit lines with drain currents flowing in the field effect transistors during a pre-charge time period, without a bit line bias voltage and with a minimized number of transistors.

Abstract: A semiconductor memory device can automatically control signal transmission power on-chip based on a wireless signal transmission. The semiconductor memory device can have a multi-chip stack structure. A power initializing method of the semiconductor memory device can comprise providing a test signal generated by a signal-providing chip to a first chip, checking whether the test signal provided to the first chip has an error, providing the checking result to the signal-providing chip, setting the power of a first signal provided to the first chip according to the checking result, and setting the power of a signal provided to a second chip adjacent to the first chip and close to the signal-providing chip using the power of the first signal.

Abstract: A memory device is provided, which includes a plurality of global bit lines, a discharge line, a switching circuit configured to connect the plurality of global bit lines to the discharge line in response to a discharge enable signal, a first discharge circuit configured to apply a first voltage that is higher than a ground voltage to the discharge line, a precharge circuit configured to apply a precharge voltage to a selected global bit line among the plurality of global bit lines, and a second discharge circuit configured to discharge the selected global bit line to a second voltage that is higher than the ground voltage.

Abstract: An up/down detection unit samples a received data signal and determines in which of first through third areas of the data signal the logic level of the data signal transitions, wherein the data sampling clock signal, the first edge sampling clock signal, and the second edge sampling clock signal are sequentially activated. A lower limit detection unit detects a lower limit of the first area if the logic level of the data signal transitions in the first area. An upper limit detection unit detects an upper limit of the third area if the logic level of the data signal transitions in the third area. A phase detection unit determines a delay amount indicating the amount by which the data signal is to be delayed according to the upper limit and lower limit detected. A buffer unit delays the data signal by the delay amount determined by the phase detection unit.

Abstract: A stacked semiconductor device includes a plurality of stacked chips, each having a plurality of elements to receive a signal. At least one first ladder main signal line for receiving the signal is arranged to pass through the chips. At least one second ladder main signal line is arranged to pass through the chips. A plurality of ladder buffers buffer the signal applied from the first ladder main signal line to the second ladder main signal line. The signal is uniformly distributed to the stacked chips using a ladder type circuit network technique.

Abstract: A semiconductor test device includes; a tester providing a first clock signal, first test data, a control signal and a first clock signal, a reference clock generating unit generating a reference clock signal, a clock converting unit receiving the reference clock signal and converting the frequency of the reference clock signal to a second clock signal in response to the control signal, and a test data converting unit receiving the first test data, converting the first test data to second test data synchronously with the second clock signal and providing the second test data to a semiconductor memory device under test.

Abstract: A semiconductor device having an electrostatic discharge (ESD) protection circuit and a method of testing the same may provided. The semiconductor device may include one or more stacked chips, each stacked chip may include a test circuit configured to output a test control signal and a selection control signal in response to a test enable signal, an internal circuit configured to perform an operation and output a plurality of test signals in response to the test control signal, at least one multiplexer (MUX) configured to select and output one of the plurality of test signals based on the selection control signal, at least one test pad configured to receive the selected test signal, and at least one electrostatic discharge (ESD) protection circuit configured to discharge static electricity applied through the test pad externally.