Patents by Inventor Young Dong Roh
Young Dong Roh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10734045Abstract: A memory system may include: a controller suitable for: generating a first clock and first pattern data having a first phase difference, in a write calibration mode, calibrating, the first phase difference depending on a second information, in a read calibration mode, detecting, a first and second value of the first and second pattern data according to the first and second clock, generating, a first information according to comparing of the first and second values, receiving by calibrating, a second phase difference generated by a memory device depending on the first information; and the memory device suitable for: generating the second clock and the second pattern data having the second phase difference, in the write calibration mode, detecting, a first and second value of the first and second pattern data according to the first and second clock, generating, the second information according to comparing of the first and second values.Type: GrantFiled: April 26, 2019Date of Patent: August 4, 2020Assignee: SK hynix Inc.Inventor: Young-Dong Roh
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Publication number: 20190252012Abstract: A memory system may include: a controller suitable for: generating a first clock and first pattern data having a first phase difference, in a write calibration mode, calibrating, the first phase difference depending on a second information, in a read calibration mode, detecting, a first and second value of the first and second pattern data according to the first and second clock, generating, a first information according to comparing of the first and second values, receiving by calibrating, a second phase difference generated by a memory device depending on the first information; and the memory device suitable for: generating the second clock and the second pattern data having the second phase difference, in the write calibration mode, detecting, a first and second value of the first and second pattern data according to the first and second clock, generating, the second information according to comparing of the first and second values.Type: ApplicationFiled: April 26, 2019Publication date: August 15, 2019Inventor: Young-Dong ROH
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Patent number: 10311925Abstract: A memory system may include: a controller suitable for: generating a first clock and first pattern data having a first phase difference, in a write calibration mode, calibrating, the first phase difference depending on a second information, in a read calibration mode, detecting, a first and second value of the first and second pattern data according to the first and second clock, generating, a first information according to comparing of the first and second values, receiving by calibrating, a second phase difference generated by a memory device depending on the first information; and the memory device suitable for: generating the second clock and the second pattern data having the second phase difference, in the write calibration mode, detecting, a first and second value of the first and second pattern data according to the first and second clock, generating, the second information according to comparing of the first and second values.Type: GrantFiled: December 5, 2017Date of Patent: June 4, 2019Assignee: SK hynix Inc.Inventor: Young-Dong Roh
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Patent number: 10248538Abstract: There are provided a controller of a semiconductor memory device, which stores data for debug processing, and an operating method of the controller. A controller for controlling a semiconductor memory device includes an event occurrence detection unit configured to detect whether an event occurs, an event information generation unit configured to generate event information in response to the detecting result from the event occurrence detection unit, and a command generation unit configured to generate a command for storing the event information in the semiconductor memory device.Type: GrantFiled: August 10, 2016Date of Patent: April 2, 2019Assignee: SK hynix Inc.Inventor: Young Dong Roh
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Patent number: 10133627Abstract: A controller includes a command generation unit suitable for generating a first read command for at least one page selected from said plurality of pages, an error correction block suitable for performing a first error correction operation to one or more code words stored in said at least one selected page in response to the first read command, and a command mirroring unit suitable for generating a mirrored command by mirroring the first read command.Type: GrantFiled: December 11, 2015Date of Patent: November 20, 2018Assignee: SK Hynix Inc.Inventors: Young Dong Roh, Se Chun Park
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Publication number: 20180308532Abstract: A memory system may include: a controller suitable for: generating a first clock and first pattern data having a first phase difference, in a write calibration mode, calibrating, the first phase difference depending on a second information, in a read calibration mode, detecting, a first and second value of the first and second pattern data according to the first and second clock, generating, a first information according to comparing of the first and second values, receiving by calibrating, a second phase difference generated by a memory device depending on the first information; and the memory device suitable for: generating the second clock and the second pattern data having the second phase difference, in the write calibration mode, detecting, a first and second value of the first and second pattern data according to the first and second clock, generating, the second information according to comparing of the first and second values.Type: ApplicationFiled: December 5, 2017Publication date: October 25, 2018Inventor: Young-Dong ROH
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Patent number: 10019173Abstract: A memory system includes a memory device comprising a plurality of memory blocks each memory block having N word line groups, N being a natural number equal to or more than 2; and a controller suitable for: selecting bad memory blocks among the memory blocks; arranging normal word line groups of the selected bad memory blocks into one or more memory-block-word-line groups each including non-conflicting N normal word line groups; and managing each of the memory-block-word-line groups as a reused memory block, the controller manages a reused block mapping table including a plurality of entries respectively corresponding to the memory-block-word-line groups, the reused block mapping table includes a plurality of logical addresses respectively corresponding to the entries, and each of the entries includes a plurality of physical address values respectively corresponding to the selected bad memory blocks having the normal word line groups included in the corresponding memory-block-word-line group.Type: GrantFiled: October 26, 2017Date of Patent: July 10, 2018Assignee: SK Hynix Inc.Inventor: Young-Dong Roh
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Patent number: 10019199Abstract: There are provided a controller coupled to a semiconductor memory device and an operating method thereof. A controller having improved operation speed includes a command generation unit for generating commands to be performed by a semiconductor memory device, a command queue for storing the commands and providing at least one command among the stored commands to the semiconductor memory device, and a command removal unit for, if the semiconductor memory device fails in the performance of the at least one command output from the main command queue, removing the at least one command and related commands of the at least one command from the command queue.Type: GrantFiled: May 20, 2016Date of Patent: July 10, 2018Assignee: SK Hynix Inc.Inventors: Se Chun Park, Young Dong Roh, Kang Wook Lee
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Publication number: 20170269874Abstract: There are provided a controller of a semiconductor memory device, which stores data for debug processing, and an operating method of the controller. A controller for controlling a semiconductor memory device includes an event occurrence detection unit configured to detect whether an event occurs, an event information generation unit configured to generate event information in response to the detecting result from the event occurrence detection unit, and a command generation unit configured to generate a command for storing the event information in the semiconductor memory device.Type: ApplicationFiled: August 10, 2016Publication date: September 21, 2017Inventor: Young Dong ROH
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Publication number: 20170192719Abstract: There are provided a controller coupled to a semiconductor memory device and an operating method thereof. A controller having improved operation speed includes a command generation unit for generating commands to be performed by a semiconductor memory device, a command queue for storing the commands and providing at least one command among the stored commands to the semiconductor memory device, and a command removal unit for, if the semiconductor memory device fails in the performance of the at least one command output from the main command queue, removing the at least one command and related commands of the at least one command from the command queue.Type: ApplicationFiled: May 20, 2016Publication date: July 6, 2017Inventors: Se Chun PARK, Young Dong ROH, Kang Wook LEE
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Patent number: 9691448Abstract: A method of operating a controller includes, determining whether an address corresponding to a program operation indicates a lower page or an upper page; waiting for a first waiting time for the program operation to the lower page when the address indicates the lower page; waiting for a second waiting time for the program operation to the upper page when the address indicates the upper page, wherein the second waiting time is longer than the first waiting time; and performing a status read operation on the semiconductor memory device after one of the first waiting time or the second waiting time.Type: GrantFiled: December 8, 2015Date of Patent: June 27, 2017Assignee: SK Hynix Inc.Inventors: Young Dong Roh, Sok Kyu Lee
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Publication number: 20170168892Abstract: A controller includes a command generation unit suitable for generating a first read command for at least one page selected from said plurality of pages, an error correction block suitable for performing a first error correction operation to one or more code words stored in said at least one selected page in response to the first read command, and a command mirroring unit suitable for generating a mirrored command by mirroring the first read command.Type: ApplicationFiled: December 11, 2015Publication date: June 15, 2017Inventors: Young Dong ROH, Se Chun PARK
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Patent number: 9542269Abstract: An operating method for controlling a semiconductor memory device according to an embodiment may include storing read commands in a command queue managed on first-in first-out basis; providing one of the read commands to the semiconductor memory device; determining whether the provided read command passes or fails based on read data, which is provided from the semiconductor memory device in response to the provided read command; and aborting remaining read commands in the command queue when the provided read command passes.Type: GrantFiled: June 29, 2015Date of Patent: January 10, 2017Assignee: SK Hynix Inc.Inventors: Young Dong Roh, Se Chun Park
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Publication number: 20160378375Abstract: A memory system includes a semiconductor memory device including a plurality of ways suitable for storing normal data and reading stored data, and a system way suitable for storing system data, and a controller suitable for controlling the semiconductor memory device to perform overall operations of the plurality of ways and an update operation of the system data of the system way.Type: ApplicationFiled: December 28, 2015Publication date: December 29, 2016Inventors: Young Dong Roh, Hyun Jung Chu
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Publication number: 20160378590Abstract: An operating method for controlling a semiconductor memory device according to an embodiment may include storing read commands in a command queue managed on first-in first-out basis; providing one of the read commands to the semiconductor memory device; determining whether the provided read command passes or fails based on read data, which is provided from the semiconductor memory device in response to the provided read command; and aborting remaining read commands in the command queue when the provided read command passes.Type: ApplicationFiled: June 29, 2015Publication date: December 29, 2016Inventors: Young Dong ROH, Se Chun PARK
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Publication number: 20160379689Abstract: A method of operating a controller includes, determining whether an address corresponding to a program operation indicates a lower page or an upper page; waiting for a first waiting time for the program operation to the lower page when the address indicates the lower page; waiting for a second waiting time for the program operation to the upper page when the address indicates the upper page, wherein the second waiting time is longer than the first waiting time; and performing a status read operation on the semiconductor memory device after one of the first waiting time or the second waiting time.Type: ApplicationFiled: December 8, 2015Publication date: December 29, 2016Inventors: Young Dong ROH, Sok Kyu LEE