Patents by Inventor Young Geon Yoo
Young Geon Yoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11360666Abstract: A storage controller includes a host interface which real-time analyzes a command received from a host, a programmable logic unit which loads an optimal image adaptively selected from a plurality of images in response to at least one of a current operating state of the storage controller and the command, and a processor which performs an operation on a nonvolatile memory device using the programmable logic unit after the optimal image is loaded.Type: GrantFiled: April 29, 2020Date of Patent: June 14, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Jung Hyun Hong, Young Jin Cho, Hyeok Jun Choe, Young Geon Yoo, Chan Ho Yoon
-
Publication number: 20220100669Abstract: A smart storage device is provided. The smart storage device includes a smart interface connected to a host device. An accelerator circuit is connected to the smart interface through a data bus conforming to a CXL.cache protocol and a CXL.mem protocol. The accelerator circuit is configured to perform acceleration computation in response to a computation command of the host device. A storage controller is connected to the smart interface through a data bus conforming to a CXL.io protocol. The storage controller is configured to control a data access operation for a storage device in response to a data access command of the host device. The accelerator circuit is directly accessible to the storage device through an internal bus connected directly to the storage controller.Type: ApplicationFiled: August 16, 2021Publication date: March 31, 2022Inventors: Hyeok Jun Choe, Youn Ho Jeon, Young Geon Yoo, Hyo-Deok Shin, I Poom Jeong
-
Publication number: 20210109655Abstract: A storage controller includes a host interface which real-time analyzes a command received from a host, a programmable logic unit which loads an optimal image adaptively selected from a plurality of images in response to at least one of a current operating state of the storage controller and the command, and a processor which performs an operation on a nonvolatile memory device using the programmable logic unit after the optimal image is loaded.Type: ApplicationFiled: April 29, 2020Publication date: April 15, 2021Inventors: JUNG HYUN HONG, YOUNG JIN CHO, HYEOK JUN CHOE, YOUNG GEON YOO, CHAN HO YOON
-
Patent number: 9904492Abstract: Provided are methods for operating a non-volatile memory controller. A method for operating a non-volatile memory controller includes dividing data provided from a host into first unit data and second unit data, encoding the first unit data into first codewords including n number of bits (n is an integer equal to or more than 1), encoding the second unit data into second codewords including n-w number of bits (w is an integer less than n and equal to or more than 1) corresponding to a bit having a value of 0 among the n number of bits of the first codewords, performing bit-to-state mapping on the first codewords and the second codewords using a predetermined bitmap, and programming the first codewords and the second codewords to a first page and a second page of a non-volatile memory, respectively.Type: GrantFiled: March 10, 2016Date of Patent: February 27, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Kyu Seol, Jun-Jin Kong, Hye-Jeong So, Hong-Rak Son, Young-Geon Yoo, Dong-Whan Lee, Dong-Sup Jin
-
Patent number: 9881671Abstract: A method is for operating a resistive memory system including a resistive memory device implemented as multi-level memory cells. The method includes setting levels of reference voltages used to determine resistance states of the multi-level memory cells, and reading data of the multi-level memory cells based on the reference voltages. A difference between the reference voltages used to determine a relatively high resistance state is greater than a difference between the reference voltages used to determine a relatively low resistance state.Type: GrantFiled: February 16, 2016Date of Patent: January 30, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Eun Chu Oh, Young-Geon Yoo, Jun Jin Kong, Hong-Rak Son, Han-Shin Shin
-
Patent number: 9570174Abstract: Provided are a coding/decoding method for use in a multi-level memory system. The coding method includes searching for a set of symbols that may generate a forbidden pattern that is set initially from an input data stream, and sticking at least one bit included in the searched set of the symbols that may generate the forbidden pattern so as not to generate the forbidden pattern.Type: GrantFiled: July 30, 2014Date of Patent: February 14, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Avner Dor, Moshe Twitto, Jun-Jin Kong, Hong-Rak Son, Young-Geon Yoo
-
Publication number: 20160299813Abstract: Provided are methods for operating a non-volatile memory controller. A method for operating a non-volatile memory controller includes dividing data provided from a host into first unit data and second unit data, encoding the first unit data into first codewords including n number of bits (n is an integer equal to or more than 1), encoding the second unit data into second codewords including n-w number of bits (w is an integer less than n and equal to or more than 1) corresponding to a bit having a value of 0 among the n number of bits of the first codewords, performing bit-to-state mapping on the first codewords and the second codewords using a predetermined bitmap, and programming the first codewords and the second codewords to a first page and a second page of a non-volatile memory, respectively.Type: ApplicationFiled: March 10, 2016Publication date: October 13, 2016Inventors: Chang-Kyu Seol, Jun-Jin Kong, Hye-Jeong So, Hong-Rak Son, Young-Geon Yoo, Dong-Whan Lee, Dong-Sup Jin
-
Publication number: 20160240250Abstract: A method is for operating a resistive memory system including a resistive memory device implemented as multi-level memory cells. The method includes setting levels of reference voltages used to determine resistance states of the multi-level memory cells, and reading data of the multi-level memory cells based on the reference voltages. A difference between the reference voltages used to determine a relatively high resistance state is greater than a difference between the reference voltages used to determine a relatively low resistance state.Type: ApplicationFiled: February 16, 2016Publication date: August 18, 2016Inventors: EUN CHU OH, YOUNG-GEON YOO, JUN JIN KONG, HONG-RAK SON, HAN-SHIN SHIN
-
Patent number: 9098391Abstract: Provided is a method of operating a memory system. The method includes programming first bit data into multiple memory cells; identifying target memory cells that are in a first state and have threshold voltages equal to or greater than a first voltage from the memory cells programmed with the first bit data; receiving second bit data which is to be programmed into the memory cells; calculating multiple third bit data by performing a first process on the second bit data; and selecting third bit data of the calculated multiple third bit data that changes a largest number of target memory cells from the first state to a second state when the memory cells are programmed with each of the multiple third bit data, respectively. The selected third bit data is programmed into the memory cells.Type: GrantFiled: October 14, 2013Date of Patent: August 4, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Seuk Yoo, Jun-Jin Kong, Chang-Kyu Seol, Hong-Rak Son, Young-Geon Yoo
-
Publication number: 20150103596Abstract: Provided are a coding/decoding method for use in a multi-level memory system. The coding method includes searching for a set of symbols that may generate a forbidden pattern that is set initially from an input data stream, and sticking at least one bit included in the searched set of the symbols that may generate the forbidden pattern so as not to generate the forbidden pattern.Type: ApplicationFiled: July 30, 2014Publication date: April 16, 2015Inventors: AVNER DOR, MOSHE TWITTO, JUN-JIN KONG, HONG-RAK SON, YOUNG-GEON YOO
-
Publication number: 20140115424Abstract: Provided is a method of operating a memory system. The method includes programming first bit data into multiple memory cells; identifying target memory cells that are in a first state and have threshold voltages equal to or greater than a first voltage from the memory cells programmed with the first bit data; receiving second bit data which is to be programmed into the memory cells; calculating multiple third bit data by performing a first process on the second bit data; and selecting third bit data of the calculated multiple third bit data that changes a largest number of target memory cells from the first state to a second state when the memory cells are programmed with each of the multiple third bit data, respectively. The selected third bit data is programmed into the memory cells.Type: ApplicationFiled: October 14, 2013Publication date: April 24, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Seuk YOO, Jun-Jin KONG, Chang-Kyu SEOL, Hong-Rak SON, Young-Geon YOO
-
Patent number: 8300746Abstract: A method of a frequency-domain equalization to jointly suppress inter-symbol interference (ISI) and data-like co-channel interference (CCI) includes receiving a transmit signal over a channel, generating a vector by sampling and converting the transmit signal to a frequency domain signal; generating an equalized vector by multiplying an equalization matrix to the vector generated by converting; generating an estimate of data vector by inverse converting the equalized vector; and recovering data included in the transmit signal based on the estimate of data vector, wherein the equalization matrix is generated by approximating a frequency domain correlation matrix. Significant computational complexity is reduced than the LMMSE equalization while resulting in almost no performance degradation compared to the LMMSE equalization.Type: GrantFiled: May 18, 2009Date of Patent: October 30, 2012Assignee: POSTECH Academy-Industry FoundationInventors: Jun Ho Cho, Young Geon Yoo
-
Publication number: 20100124266Abstract: A method of a frequency-domain equalization to jointly suppress inter-symbol interference (ISI) and data-like co-channel interference (CCI) includes receiving a transmit signal over a channel, generating a vector by sampling and converting the transmit signal to a frequency domain signal; generating an equalized vector by multiplying an equalization matrix to the vector generated by converting; generating an estimate of data vector by inverse converting the equalized vector; and recovering data included in the transmit signal based on the estimate of data vector, wherein the equalization matrix is generated by approximating a frequency domain correlation matrix. Significant computational complexity is reduced than the LMMSE equalization while resulting in almost no performance degradation compared to the LMMSE equalization.Type: ApplicationFiled: May 18, 2009Publication date: May 20, 2010Applicant: POSTECH Academy-Industry FoundationInventors: Joon Ho CHO, Young Geon Yoo