Abstract: Reducing coupling and mismatch in multi-core VCOs, including: arranging a plurality of inductors in a plurality of VCO cores in a parallel differential inductor configuration with shared leads to form a single node, wherein the plurality of inductors includes at least a first inductor and a second inductor; connecting power/ground traces to the first inductor from a first side only; and connecting the power/ground traces to the second inductor from another side different from the first side only to avoid making a current loop.

Abstract: The present invention relates to a printed circuit board, which includes: a connection pad consisting of a seed layer formed on an upper surface of an insulating layer and a metal layer formed on an upper surface of the seed layer; a first plating layer formed to surround the connection pad; and a second plating layer formed on an upper surface of the first plating layer except a side surface of the first plating layer, and a method for manufacturing the same.

Abstract: The present invention relates to a printed circuit board which includes: a solder pad on which a solder ball is mounted; an insulator formed on the solder pad; and a protrusion formed under the insulator to support the solder ball when mounting the solder ball and can stably mount the solder ball.

Abstract: A transformer is described. The transformer includes a primary coil and a first secondary coil. A first coupling occurs between the first secondary coil and the primary coil. The transformer also includes a second secondary coil. A second coupling occurs between the second secondary coil and the primary coil. The first secondary coil is separated from the second secondary coil to prevent coupling between the first secondary coil and the second secondary coil. A first width of the first secondary coil is configured independently of a second width of the second secondary coil.

Abstract: Disclosed herein is a printed circuit board including: an insulating layer having first and second surfaces; a first circuit layer formed on the first surface of the insulating layer and including at least one first circuit pattern; a second circuit layer formed on the first circuit layer and including at least one second circuit pattern; and an insulating film formed in an insulating region of the first and second circuit layers.

Abstract: An integrated circuit is described. The integrated circuit includes a global positioning system core that generates a GPS clock signal using an inductor-capacitor voltage controlled oscillator. The integrated circuit also includes a transceiver core configured to use the GPS clock signal. The transceiver core may not include a voltage controlled oscillator.

Abstract: Disclosed herein are a printed circuit board (PCB) and a method of manufacturing the same. The PCB includes a core layer, metal bumps embedded in the core layer, one surface of the metal bumps being opened to the outside, and a solder resist layer including an opening is manufactured by a separating substrate manufacture method. In the PCB, empty space between the bumps is filled with an insulating material instead of solder resist, and thus, a problem in terms of an empty space between bumps is addressed without requiring a new solder resist process.

Abstract: An integrated circuit is disclosed. The integrated circuit includes a primary coil. The integrated circuit also includes a first secondary coil that acts as a first transformer with the primary coil. The integrated circuit further includes a second secondary coil that acts as a second transformer with the primary coil. The primary coil, the first secondary coil and the second secondary coil have a layout on the integrated circuit to minimize coupling between the first secondary coil and the second secondary coil.

Abstract: An output portion of a charge pump receives control signals from a phase frequency detector and in response outputs positive current pulses and negative current pulses to a loop filter. A current control portion of the charge pump controls the output portion such that the magnitudes of the positive and negative current pulses are the same. Within the current control portion there is a “Charge Pump Output Voltage Replica Node” (CPOVRN). The voltage on this CPOVRN is maintained to be the same as a voltage on the charge pump output node. A capacitor leakage compensation circuit indirectly senses the voltage across a leaking capacitor of the loop filter by sensing the voltage on the CPOVRN. The compensation circuit imposes the sensed voltage across a replica capacitor, mirrors a current leaking through the replica, and supplies the mirrored current in the form of a compensation current to the leaking capacitor.

Abstract: A semiconductor package includes a lead structure upon which a semiconductor die is mounted with at least some portion of at least some of the leads extending to, at, or across an axis or axis of the package to militate against thermally induced growth of the package and the reduce or minimize strain within the package and reliability issue associated therewith.

Abstract: An integrated circuit is disclosed. The integrated circuit includes a primary coil. The integrated circuit also includes a first secondary coil that acts as a first transformer with the primary coil. The integrated circuit further includes a second secondary coil that acts as a second transformer with the primary coil. The primary coil, the first secondary coil and the second secondary coil have a layout on the integrated circuit to minimize coupling between the first secondary coil and the second secondary coil.

Abstract: A method of writing partial page data in a non-volatile memory device includes, reading data from a second block when the size of a last page of data to be written in a page of a first block is smaller than a size of the page of the first block, wherein a size of the read data is given by the size of the page of the first block minus the size of the last page of data; storing together data of the last page and the data read from the second block in a buffer; and writing the data stored in the buffer in the first block.

Abstract: An integrated circuit is described. The integrated circuit includes a global positioning system core that generates a GPS clock signal using an inductor-capacitor voltage controlled oscillator. The integrated circuit also includes a transceiver core configured to use the GPS clock signal. The transceiver core may not include a voltage controlled oscillator.

Abstract: A radio frequency identifying device minimizes a null point area within a radiation pattern by horizontally or vertically vibrating an antenna plate radiating a radio frequency beam by using at least one vibration motor.

Abstract: Provided is a method and system for measuring traffic quality in distribution using test mail into which a radio frequency identity tag is inserted. The system accepts at least one test distribution piece including a tag, and collects information of test distribution by sensing a tag included with the test distribution piece at measuring points for measuring a time from acceptance to delivery of a general distribution piece. The system generates a processing rate and a delivery rate of distribution based on information of the test distribution pieces collected from the measuring points.

Abstract: A first transmission line is formed on a first surface of a substrate. A first end of the first transmission line is connected to a transmission line of an unbalanced line. A second end is connected to a first transmission line of a balanced line. A second transmission line extends from a first end of the unbalanced line, alongside the first transmission line and spaced therefrom, and is connected to a second of the transmission lines of the balanced line. A ground plane is formed on a second surface of the substrate, extends from a first end of the balanced line, and is formed along the second transmission line to which the ground plane is connected through one or more vias. A width of a portion of the ground plane adjacent to the unbalanced line is greater than a portion thereof adjacent to the balanced line.

Abstract: An apparatus, memory device controller and method of controlling a memory device are provided. The example apparatus may include a bad block bitmap referencing unit configured to obtain bad block information from a bad block bitmap based on a given memory address, the given memory address being one of a logical memory address and a physical memory address corresponding to the logical memory address, the bad block information indicating whether a given memory block corresponding to the given memory address is a bad block and a memory mapping unit configured to obtain the physical memory address corresponding to the logical memory address, and configured to obtain a reserved physical memory address corresponding to the physical memory address if the bad block information indicates that the given memory block is a bad block. In an example, the apparatus may be embodied as a memory device controller including a flash translation layer (FTL).

Abstract: A bottom unit including a bottom unit semiconductor chip is mounted to a circuit board and one or more top elements such as packaged semiconductor chips are mounted to the bottom unit. Both mounting operations can be performed using the same techniques as commonly employed for mounting components to a circuit board. Ordinary packaged chips can be employed as the top elements, thereby reducing the cost of the assembly and allowing customization of the assembly by selecting packaged chips. The assembly achieves benefits similar to those obtained with a preassembled stacked chip unit, but without the expense of special handling of the bare dies included in the packaged chips.

Abstract: A radio frequency identifying device minimizes a null point area within a radiation pattern by horizontally or vertically vibrating an antenna plate radiating a radio frequency beam by using at least one vibration motor.

Abstract: A connection component for mounting a chip or other microelectronic element is formed from a starting unit including posts projecting from a dielectric element by crushing or otherwise reducing the height of at least some of the posts.