Abstract: Disclosed is a method for setting sequential ID to a multi-slave BMS in a battery pack, the battery pack including N (N: natural number of 2 or more) slave BMSs having sequential physical locations to control a battery module containing at least one battery and a main BMS to control the N slave BMSs.

Abstract: A snap ring for fishing implements is provided. The snap ring includes a hook-like body having an opening on a portion thereof, a rotary shaft coupled on one side to a portion of the body such that the rotary shaft is rotatable around the opening, a hollow guide into which the rotary shaft is fitted and slides along, and a guide spring provided between the rotary shaft and the guide to elastically support the guide against the rotary shaft.

Abstract: Disclosed is an apparatus for agitating a liquid hardener used for improving soft ground. The apparatus comprises a storage tank section formed with an introduction part and having storage tanks in which mixing impellers are arranged, and transparent indicator tubes which are communicated with the storage tanks each; an agitation tank section positioned underneath the storage tank section and having agitation tanks, supply valves which are installed on the agitation tanks, and agitation impellers which are respectively arranged in the agitation tanks; a liquid mixture supply section having connection pipes which are connected to the storage tanks, a supply pipe which is connected to the connection pipes, and distribution pipes which are connected to the supply pipe; and a cleaning water tank section positioned in front of the agitation tank section and having a plurality of cleaning water tanks.

Abstract: Disclosed is an apparatus for agitating a liquid hardener used for improving soft ground. The apparatus comprises a storage tank section formed with an introduction part and having storage tanks in which mixing impellers are arranged, and transparent indicator tubes which are communicated with the storage tanks each; an agitation tank section positioned underneath the storage tank section and having agitation tanks, supply valves which are installed on the agitation tanks, and agitation impellers which are respectively arranged in the agitation tanks; a liquid mixture supply section having connection pipes which are connected to the storage tanks, a supply pipe which is connected to the connection pipes, and distribution pipes which are connected to the supply pipe; and a cleaning water tank section positioned in front of the agitation tank section and having a plurality of cleaning water tanks.

Abstract: A method for fabricating a semiconductor device in which channel resistance is prevented from occurring due to impurity ion diffusion and gate resistance is reduced, thereby improving the speed characteristic of the device. The method for forming a dual gate of a semiconductor device includes the steps of forming a polysilicon layer on a semiconductor substrate; selectively forming an impurity ion layer of a first conductive type and an impurity ion layer of a second conductive type on a lower surface to the polysilicon layer; polishing the polysilicon layer; forming a low resistance metal layer on the polished polysilicon layer; forming a first gate electrode and a second gate electrode by an etching process using a gate mask; and forming source/drain regions of the first conductive type in the substrate at both sides of the first gate electrode and source/drain regions of the second conductive type in the substrate at both sides of the second gate electrode.

Abstract: A method for manufacturing a semiconductor device capable of performing a writing operation with a small amount of current by forming a thin oxide film on the surface a word line being used as a write line so as to reduce the distance between an MTJ cell and the word line includes the steps of forming a word line on a semiconductor substrate, wherein the word line is used as a write line, forming a planarized layer insulating film exposing the surface of the word line, forming a dielectric film on the surface of the word line, forming a seed layer connected to the word line through the dielectric film and configuring a cell on the top of the seed layer and in an upper portion of the word line.

Abstract: A memory device and a fabrication method therefor. In order to improve an operation property of a magnetic RAM (abbreviated as ‘MRAM’) having a higher speed than an SRAM, integration as high as a DRAM, and a property of a nonvolatile memory such as a flash memory, an oxide film is thinly formed on a second word line which is a write line, and an MTJ cell is formed according to a succeeding process. The MRAM is formed by reducing a distance between the write line and the MTJ cell. It is thus possible to perform a write operation with a small current.

Abstract: A method for manufacturing a semiconductor device capable of performing a writing operation with a small amount of current by forming a thin oxide film on the surface a word line being used as a write line so as to reduce the distance between an MTJ cell and the word line includes the steps of forming a word line on a semiconductor substrate, wherein the word line is used as a write line, forming a planarized layer insulating film exposing the surface of the word line, forming a dielectric film on the surface of the word line, forming a seed layer connected to the word line through the dielectric film and configuring a cell on the top of the seed layer and in an upper portion of the word line.

Abstract: A method for fabricating a semiconductor device in which channel resistance is prevented from occurring due to impurity ion diffusion and gate resistance is reduced, thereby improving the speed characteristic of the device. The method for forming a dual gate of a semiconductor device includes the steps of forming a polysilicon layer on a semiconductor substrate; selectively forming an impurity ion layer of a first conductive type and an impurity ion layer of a second conductive type on a lower surface of the polysilicon layer; polishing the polysilicon layer; forming a low resistance metal layer on the polished polysilicon layer; forming a first gate electrode and a second gate electrode by an etching process using a gate mask; and forming source/drain regions of the first conductive type in the substrate at both sides of the first gate electrode and source/drain regions of the second conductive type in the substrate at both sides of the second gate electrode.

Abstract: A fabrication method for a semiconductor device capable of adjusting a thickness of each portion of gate insulating film at both sides of a gate, which includes the steps of: providing a semiconductor substrate having a first region and a second region; forming a gate insulating film on the substrate; forming a conductive layer on the gate insulating film and patterning the conductive layer, for thereby forming a first gate and a second gate on the first and second regions, respectively; forming impurity areas in the first region at both sides of the first gate in order to reduce the velocity of oxidation; applying a re-oxidation process to the gate insulating film, for thereby forming each portion of the gate insulating film at both sides of the first gate thinner than each portion of the gate insulating film at both sides of the second gate; and respectively forming a source/drain region at both sides of the first and second gates.

Abstract: Semiconductor device and method for fabricating the same, is disclosed, which can maintain a threshold voltage constant despite of decreased channel width, the device including a first, and a second conductive type wells in a substrate, a first, and a second gate insulating films on the first, and the second conductive type wells, a first gate electrode on the first gate insulating film, the first gate electrode being doped with a second conductive type except for edges of the first gate electrode in a channel width direction counter doped with a first conductive type, a second gate electrode on the second gate insulating film, the second gate electrode being doped with a first conductive type except for edges of the second gate electrode in a channel width direction counter doped with a second conductive type, and isolating regions formed between the first, and second conductive type wells, the first, and second gate insulating films, and the first, and second gate electrodes.

Abstract: An ESD (Electro-Static Discharge) protection circuit includes a semiconductor substrate having an active region and field regions, isolating films formed in the field regions, a gate insulating film formed on the active region, and a gate electrode formed on the gate insulating film, first and second heavily doped impurity regions formed in a surface of the semiconductor substrate at sides of the gate electrode, a plurality of dummy gate electrodes formed on the second heavily doped impurity region and offset from the gate electrode, insulating sidewalls formed at the sides of the gate electrode and at sides of each of the dummy gate electrodes, and salicide films formed on a surface of the gate electrode, on surfaces of each of the dummy gate electrodes and on a surface of the first heavily doped impurity region.

Abstract: A semiconductor device and a fabrication method thereof using a silicon-on-insulator (SOI) technique has an object of improving electrostatic discharge (ESD) protection capability. In order to achieve the object, there are provided the steps of relatively shallowly forming a portion of a buried oxide film in a first region in a silicon substrate for fabricating an integrated circuit device, relatively deep forming the other portion of the buried oxide film in a second region for fabricating an ESD protection device, for thereby fabricating an SOI substrate, and forming the integrated circuit device on a predetermined portion of the first region of the SOI substrate and the ESD protection device on a predetermined portion of the second region.

Abstract: A semiconductor device isolation method includes sequentially forming a first insulating film and a second insulating film on a semiconductor substrate, exposing a predetermined portion of the surface of the semiconductor substrate, forming a third insulating on the exposed surface of the semiconductor substrate and the second insulating film, forming sidewall spacers composed of the third insulating film at the sidewall surfaces of the first and second insulating films, forming a trench by performing an etching by a predetermined depth using the sidewall spacers as a mask, removing the sidewall spacers, filling a high density plasma chemical vapor deposition (HDP CVD) oxide in the trench, and removing the first and second insulating films.

Abstract: A semiconductor device isolation structure includes a trench formed in a substrate vertically from the major surface of the substrate, a trench plug for filling the trench, and a buried insulation region formed under the trench adjacent thereto, and a method of the same includes the steps of forming a trench in a substrate and vertically from the major surface of the substrate, selectively implanting oxide ions under the trench of the substrate, and forming a trench plug so as to fill the trench.

Abstract: A method of fabricating a semiconductor device having a trench isolation structure includes forming an isolation region including a trench and a trench plug for filling the trench so as to define active regions on a substrate, a part of the trench plug projecting upward from the surface of the substrate, forming sidewall spacers from an oxidative material on the sidewalls of the projecting portion of the trench plug, and oxidating the surface of the active region of the substrate and the sidewall spacers so as to form a gate insulating layer extending to the upper part of the active region of the substrate and the side surfaces of the trench plug.

Abstract: A method of fabricating a phase inverted mask comprising the steps of forming a shielding layer pattern on a substrate, injecting oxygen ions into a surface of the shielding layer pattern, and converting the shielding layer pattern having the oxygen ions injected therein into an oxidation layer to thereby form a phase inverted layer.