Abstract: A method includes forming a first package structure including a first connection member including a first redistribution layer, a first frame having a first through-portion, a first semiconductor chip having a connection pad electrically connected to the first redistribution layer, and a first encapsulant covering a portion of each of the first frame and the first semiconductor chip, forming a second package structure including a second connection member including a second redistribution layer, a second semiconductor chip having a second connection pad, and a second encapsulant covering a portion of the second semiconductor chip, forming a first through-via, the first through-via electrically connecting to the second redistribution layer, and laminating the first package structure on the second package structure.

Abstract: Disclosed is an inductor device and method of manufacturing the same. The inductor device includes an insulating layer, a coil pattern formed on two opposing surfaces of the insulating layer, a first insulating film and a second insulating film formed with different insulating materials on the coil pattern, and a magnetic member formed to enclose the insulating layer, the coil pattern and the first and the second insulating films. By forming thin dual insulating films having a high adhesive strength and breaking strength on an inductor coil, it is possible to improve Ls characteristics of the inductor device and increase the inductance.

Abstract: A semiconductor package including a core structure, in which a first and second semiconductor chips and passive components are embedded, a connection structure disposed on a first side of the core structure, and including a redistribution layer electrically connected to the first and second semiconductor chips and the passive components, and a metal pattern layer and a backside wiring layer disposed on a second side of the core structure opposing the first side, and spaced apart from each other. The core structure includes a first metal layer surrounding the first semiconductor chip, a second metal layer surrounding the first semiconductor chip, and the first metal layer, a third metal layer surrounding the second semiconductor chip, and a fourth metal layer surrounding the second semiconductor chip, the passive components, and the third metal layer, and each of the first to fourth metal layers is electrically connected to the metal pattern layer.

Abstract: A method for manufacturing a semiconductor package includes disposing a semiconductor chip having contact pads, and a connection structure around the semiconductor chip on a supporting substrate, with the contact pads facing the supporting substrate, forming an encapsulant encapsulating the semiconductor chip and the connection structure on the supporting substrate, embedding a wiring pattern having a connection portion in the encapsulant, the connection portion having a connection hole, forming a through hole penetrating the encapsulant in the connection hole, the through hole exposing a portion of an upper surface of the connection structure, and forming a conductive via in the through hole, the conductive via connecting the wiring pattern to the connection structure.

Abstract: A method including forming a frame having an opening, forming a first metal layer, forming a first encapsulant, forming an insulation layer on the first metal layer, forming a first through-hole and a second through-hole penetrating the insulation layer and the first encapsulant, forming a second metal layer and a third metal layer, forming a second encapsulant, forming a first metal via and a second metal via penetrating the second encapsulant and a metal pattern layer on the second encapsulant, and forming a connection structure. The first metal layer and the second metal layer respectively are formed to extend to a surface of each of the first encapsulant and the frame, facing the metal pattern layer, and the first metal layer and the second metal layer are connected to the metal pattern layer through the first metal via and the second metal via having heights different from each other.

Abstract: A semiconductor package includes a frame having a wiring structure and having a recess portion, a semiconductor chip having an active surface with a connection pad disposed thereon and disposed in the recess portion, an encapsulant sealing the semiconductor chip, and a redistribution layer having a first via connected to the connection and a second via connected to a portion of the wiring structure. The semiconductor chip includes a protective insulating film disposed on the active surface and having an opening exposing a region of the connection pad, and a redistribution capping layer connected to the region of the connection pad and extending onto the protective insulating film, and a surface of the redistribution capping layer is substantially the same level as a surface of the portion of the wiring structure, exposed from the first surface.

Abstract: A semiconductor package includes a semiconductor chip; a connection member having a first surface on which the semiconductor chip is disposed and a second surface opposing the first surface, an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip, a passivation layer on the second surface of the connection member; and an UBM layer partially embedded in the passivation layer, wherein the UBM layer includes an UBM via embedded in the passivation layer and connected to the redistribution layer of the connection member and an UBM pad connected to the UBM via and protruding from a surface of the passivation layer, and a width of a portion of the UBM via in contact with the UBM pad is narrower than a width of a portion of the UBM via in contact with the redistribution layer.

Abstract: A semiconductor package includes a frame having a cavity and having a wiring structure connecting first and second surfaces opposing each other; a connection structure disposed on the first surface of the frame and including a first redistribution layer connected to the wiring structure; a semiconductor chip disposed in the cavity and having a connection pad connected to the first redistribution layer; an encapsulant encapsulating the semiconductor chip; and a second redistribution layer having a redistribution pattern and a connection via connecting the wiring structure and the redistribution pattern. The connection via includes a first via connected to the wiring structure and a second via disposed on the first via and connected to the redistribution pattern, a lower surface of the second via has an area larger than an area of an upper surface of the first via.

Abstract: A method includes forming a first package structure including a first connection member including a first redistribution layer, a first frame having a first through-portion, a first semiconductor chip having a connection pad electrically connected to the first redistribution layer, and a first encapsulant covering a portion of each of the first frame and the first semiconductor chip, forming a second package structure including a second connection member including a second redistribution layer, a second semiconductor chip having a second connection pad, and a second encapsulant covering a portion of the second semiconductor chip, forming a first through-via, the first through-via electrically connecting to the second redistribution layer, and laminating the first package structure on the second package structure.

Abstract: A method including forming a frame having an opening, forming a first metal layer, forming a first encapsulant, forming an insulation layer on the first metal layer, forming a first through-hole and a second through-hole penetrating the insulation layer and the first encapsulant, forming a second metal layer and a third metal layer, forming a second encapsulant, forming a first metal via and a second metal via penetrating the second encapsulant and a metal pattern layer on the second encapsulant, and forming a connection structure. The first metal layer and the second metal layer respectively are formed to extend to a surface of each of the first encapsulant and the frame, facing the metal pattern layer, and the first metal layer and the second metal layer are connected to the metal pattern layer through the first metal via and the second metal via having heights different from each other.

Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a second connection member disposed on the first connection member and the active surface of the semiconductor chip; and a heat dissipation layer embedded in the encapsulant so that one surface thereof is exposed. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip.

Abstract: A semiconductor package includes a connection structure including an insulating layer, a redistribution layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the redistribution layer, a frame disposed on the connection structure and having a through-hole, a semiconductor chip disposed in the through-hole on the connection structure and having a connection pad disposed to face the connection structure, and a passive component disposed on the frame.

Abstract: A semiconductor package includes a first connection member including a first redistribution layer, a first frame disposed on the first connection member, a first semiconductor chip disposed on a first through-portion and having a connection pad, a first encapsulant covering a portion of each of the first frame and the first semiconductor chip and filling at least a portion of the first through-portion, a second connection member disposed on the first encapsulant and including a second redistribution layer, a second semiconductor chip disposed on the second connection member and having a second connection pad, a second encapsulant covering a portion of the second semiconductor chip, and a first through-via penetrating through the first frame, the first encapsulant, and a portion of the first connection member, and electrically connecting the first and second redistribution layers to each other.

Abstract: A semiconductor package includes a core structure having a first through-hole and including a frame having an opening, a passive component disposed in the opening, a first encapsulant covering the frame and the passive component, a first metal layer disposed on an inner surface of the first through-hole, and a second metal layer disposed on an inner surface of the opening; a first semiconductor chip disposed in the first through-hole and having a first connection pad; a second encapsulant covering the core structure and the first semiconductor chip; a connection structure disposed on the core structure and the first semiconductor chip and including a redistribution layer; and a metal pattern layer disposed on the second encapsulant. The first and second metal layers are connected to the metal pattern layer through first and second metal vias having heights different from each other.

Abstract: A semiconductor package includes a frame having first and second through-portions, first and second semiconductor chips, respectively in the first and second through-portions, each having a first surface, on which a connection pad is disposed, a first encapsulant covering at least a portion of the first and second semiconductor chips, a first connection member on the first and second semiconductor chips including a first redistribution layer electrically connected to the connection pads of the first and second semiconductor chips and a heat dissipation pattern layer, at least one passive component above the first semiconductor chip on the first connection member, and at least one heat dissipation structure above the second semiconductor chip on the first connection member and connected to the heat dissipation pattern layer.

Abstract: A method for manufacturing a semiconductor package includes disposing a semiconductor chip having contact pads, and a connection structure around the semiconductor chip on a supporting substrate, with the contact pads facing the supporting substrate, forming an encapsulant encapsulating the semiconductor chip and the connection structure on the supporting substrate, embedding a wiring pattern having a connection portion in the encapsulant, the connection portion having a connection hole, forming a through hole penetrating the encapsulant in the connection hole, the through hole exposing a portion of an upper surface of the connection structure, and forming a conductive via in the through hole, the conductive via connecting the wiring pattern to the connection structure.

Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface, and disposed in the recess portion so that the inactive surface is connected to the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers of the frame and the connection pads of the semiconductor chip to each other, wherein the stopper layer includes an insulating material.

Abstract: A semiconductor package includes a supporting member that has a cavity and includes a wiring structure connecting first and second surfaces opposing each other. A connection member is on the second surface of the supporting member and includes a first redistribution layer connected to the wiring structure. A semiconductor chip is on the connection member in the cavity and has connection pads connected to the first redistribution layer. An encapsulant encapsulates the semiconductor chip disposed in the cavity and covers the first surface of the supporting member. A second redistribution layer includes wiring patterns embedded in the encapsulant and has exposed surfaces and connection vias that penetrate through the encapsulant to connect the wiring structure and the wiring patterns to each other.

Abstract: A semiconductor package includes a frame having a wiring structure and having a recess portion, a semiconductor chip having an active surface with a connection pad disposed thereon and disposed in the recess portion, an encapsulant sealing the semiconductor chip, and a redistribution layer having a first via connected to the connection and a second via connected to a portion of the wiring structure. The semiconductor chip includes a protective insulating film disposed on the active surface and having an opening exposing a region of the connection pad, and a redistribution capping layer connected to the region of the connection pad and extending onto the protective insulating film, and a surface of the redistribution capping layer is substantially the same level as a surface of the portion of the wiring structure, exposed from the first surface.

Abstract: A semiconductor device includes a semiconductor chip having an active surface having connection pads disposed thereon; an encapsulant encapsulating at least portions of the semiconductor chip, a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads, a passivation layer disposed on the connection member, and an under bump metallurgy (UBM) layer embedded in the passivation layer and electrically connected to the redistribution layer of the connection member. The UBM layer includes a UBM pad embedded in the passivation layer and having a recess portion, and a UBM via penetrating through a portion of the passivation layer and electrically connecting the redistribution layer of the connection member and the UBM pad to each other.