Abstract: Open circuit voltage of a photovoltaic device including a p-i-n junction including amorphous silicon-containing semiconductor materials is increased by a high power plasma treatment on an amorphous p-doped silicon-containing semiconductor layer before depositing an amorphous intrinsic silicon-containing semiconductor layer. The high power plasma treatment deposits a thin layer of nanocrystalline silicon-containing semiconductor material or converts a surface layer of the amorphous p-doped silicon containing layer into a thin nanocrystalline silicon-containing semiconductor layer. After deposition of an intrinsic amorphous silicon layer, the thin nanocrystalline silicon-containing semiconductor layer functions as an interfacial nanocrystalline silicon-containing semiconductor layer located at a p-i junction.

Abstract: A tunneling layer is provided between a transparent conductive material and a p-doped semiconductor layer of a photovoltaic device. The tunneling layer is comprised of stoichiometric oxides which are formed when an upper surface of the transparent conductive material is subjected to one of the surface modification techniques of this disclosure. The surface modification techniques oxidize the dangling metal bonds of the transparent conductive material. The tunneling layer acts as a protective layer for the transparent conductive material. Moreover, the tunneling layer improves the interface between the transparent conductive material and the p-doped semiconductor layer. The improved interface that exists between the transparent conductive material and the p-doped semiconductor layer results in enhanced properties of the resultant photovoltaic device containing the same. In some embodiments, a high quality single junction solar cell can be provided by this disclosure that has a very well defined interface.

Abstract: An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention.

Abstract: Provided are polycarbosilane and a method of producing the same. The polycarbosilane contains an allyl group, and thus can be cured by UV absorption when not exposed to the air.

Abstract: Provided is a cell packaging material having a layered structure of one or more layers, wherein at least one layer includes a flame retardant, a coating layer imparted with flame resistance, or both. In the cell packaging material, a cell itself does not include any flame resistant film or flame retardant. Therefore, it is possible to provide a cell with flame resistance while not increasing the cell volume or not affecting the cell operation.

Abstract: The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.

Abstract: Provided is a method of simulating various viscoelastic fluids having viscosity, elasticity, and plasticity, based on smoothed particle hydrodynamics (SPH), which is widely used in fluid simulation using particles. Artificial forces related with viscosity, elasticity, and plasticity are added to address fundamental numerical limitations of a SPH method due to use of particle approximation and to improve expression of characterized motions of a viscoelastic fluid. Since the artificial forces are added, and parameters are adjusted according to the adding of the artificial forces, a fluid can be realistically expressed, and the control of a fluid motion is facilitated.

Abstract: A vertical stack of a first silicon germanium alloy layer, a second epitaxial silicon layer, a second silicon germanium layer, and a germanium layer are formed epitaxially on a top surface of a first epitaxial silicon layer. The second epitaxial silicon layer, the second silicon germanium layer, and the germanium layer are patterned and encapsulated by a dielectric cap portion, a dielectric spacer, and the first silicon germanium layer. The silicon germanium layer is removed between the first and second silicon layers to form a silicon germanium mesa structure that structurally support an overhanging structure comprising a stack of a silicon portion, a silicon germanium alloy portion, a germanium photodetector, and a dielectric cap portion. The germanium photodetector is suspended by the silicon germanium mesa structure and does not abut a silicon waveguide. Germanium diffusion into the silicon waveguide and defect density in the germanium detector are minimized.

Abstract: Disclosed are a label and a method of manufacturing the same, the label comprising: a first base film; a first ink layer formed on the exterior top part of the first base film, and comprising a metal or metal oxide that changes from its original color to another color by being oxidized by a laser; and a resin coating layer coated on the first ink layer to protect the first ink layer, wherein the laser passing through a part or the whole of the resin coating layer is transmitted to the first ink layer. According to the present invention, there is no oxidation residue; thus, the efficiency of marking is excellent and any possibility of change in quality due to aging can be eliminated. In addition, the color rendering is excellent, and the scratch resistance, chemical resistance and heat resistance are superior.

Abstract: Disclosed is a protective film-integrated pouch wherein a protective film to protect a display panel and a bag to cover and package the display panel are integrally formed. The protective film-integrated pouch includes a rectangular body, including upper and lower layers, the body having three sealed edges and one opened edge to define an opening, allowing insertion of a display panel into the pouch, wherein each of the upper layer and the lower layer includes a base layer made of a metallic material, an outer surface layer disposed on the base layer, and an inner surface layer disposed on the outer surface layer, wherein the inner surface layer contacts the display panel and is made of a mixed polyethylene resin.

Abstract: Disclosed is a biodegradable starch bowl prepared by heating and pressurizing a composition for the biodegradable starch bowl comprising unmodified starch of 20˜60 wt. %; pulp fiber powder of 5˜30 wt. %; solvent of 30˜60 wt. %; photo catalyst of 0.1˜2.0 wt. %; preservative of 0.01˜1 wt. %; and releasing agent of 0.5˜5 wt. % to have a desired shape, and a biodegradable film being attached on the inner surface of the bowl. The biodegradable starch bowl according to the present invention has an improved sterilizing property, deodorizing property, preservative property, releasing property, water-resistance and strength.

Abstract: A vertical stack of a first silicon germanium alloy layer, a second epitaxial silicon layer, a second silicon germanium layer, and a germanium layer are formed epitaxially on a top surface of a first epitaxial silicon layer. The second epitaxial silicon layer, the second silicon germanium layer, and the germanium layer are patterned and encapsulated by a dielectric cap portion, a dielectric spacer, and the first silicon germanium layer. The silicon germanium layer is removed between the first and second silicon layers to form a silicon germanium mesa structure that structurally support an overhanging structure comprising a stack of a silicon portion, a silicon germanium alloy portion, a germanium photodetector, and a dielectric cap portion. The germanium photodetector is suspended by the silicon germanium mesa structure and does not abut a silicon waveguide. Germanium diffusion into the silicon waveguide and defect density in the germanium detector are minimized.

Abstract: Current may be passed through an n-doped semiconductor region, a recessed metal semiconductor alloy portion, and a p-doped semiconductor region so that the diffusion of majority charge carriers in the doped semiconductor regions transfers heat from or into the semiconductor waveguide through Peltier-Seebeck effect. Further, a temperature control device may be configured to include a metal semiconductor alloy region located in proximity to an optoelectronic device, a first semiconductor region having a p-type doping, and a second semiconductor region having an n-type doping. The temperature of the optoelectronic device may thus be controlled to stabilize the performance of the optoelectronic device.

Abstract: A method of fabricating semiconductor structure is provided in which at least one nFET device and a least one pFET device are formed on a semiconductor substrate. Each device region formed includes a dielectric stack that has a net dielectric constant equal to or greater than silicon dioxide. Gate stacks are provided on each of the dielectric stacks, wherein one of the gate stacks includes a metal gate electrode located atop a surface of a thinned polygate electrode.

Abstract: A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer and an oxygen scavenging layer on the high-k dielectric layer.

Abstract: Disclosed is a label comprising a substrate film, or a substrate film and an intermediate film, wherein either or both of the substrate film and the intermediate film have through-holes, and a method for preparing the same. The method for preparing the label causes no generation of defects, and shows an excellent production rate and work efficiency. The label has no possibility of forgery, and shows clear marking characteristics. In addition, the label has a simple structure and excellent printability and cost efficiency, causes no degradation of the quality with time, shows high chemical resistance and heat resistance, is free from various contaminants during use, and is provided with low initial adhesion but high permanent adhesion.

Abstract: A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) are formed by patterning of a gate dielectric layer, a thin silicon layer, and a silicon-germanium alloy layer. After formation of the source/drain regions and gate spacers, silicon germanium alloy portions are removed from gate stacks. A dielectric layer is formed and patterned to cover an NFET gate electrode, while exposing a thin silicon portion for a PFET. Germanium is selectively deposited on semiconductor surfaces including the exposed silicon portion. The dielectric layer is removed and a metal layer is deposited and reacted with underlying semiconductor material to form a metal silicide for a gate electrode of the NFET, while forming a metal silicide-germanide alloy for a gate electrode of the PFET.

Abstract: Disclosed is a protective film-integrated pouch wherein a protective film to protect a display panel and a bag to cover and package the display panel are integrally formed. The protective film-integrated pouch includes a rectangular body, including upper and lower layers, the body having three sealed edges and one opened edge to define an opening, allowing insertion of a display panel into the pouch, wherein each of the upper layer and the lower layer includes a base layer made of a metallic material, an outer surface layer disposed on the base layer, and an inner surface layer disposed on the outer surface layer, wherein the inner surface layer contacts the display panel and is made of a mixed polyethylene resin.

Abstract: A method for calculating a force acting on an interface between immiscible fluids in an SPH (Smoothed Particle Hydrodynamics) based fluid simulation includes: calculating a force caused by viscosities of the fluids; calculating a force caused by pressures of the fluids; calculating an external force applied to the fluids from outside; and calculating an interactive force caused by interaction between the fluids. The force acting on the interface between the immiscible fluids are obtained by using sum of the force caused by the viscosities, the force caused by the pressures, the external force and the interactive force. The interactive force is a surface tensional force calculated based on a pressure acting on the interface between the fluids.

Abstract: An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention.