Abstract: An organic electric element according to an embodiment of the present disclosure includes a first electrode, a second electrode, and an organic material layer formed between the first electrode and the second electrode. The organic material layer may include a plurality of light-emitting auxiliary layers and the LUMO/HOMO energy levels of the plurality of light-emitting auxiliary layers are limited to specific conditions in relation to the neighboring organic material layers, thereby the driving voltage, the luminous efficiency and the lifetime of the organic electric element can be improved.

Abstract: The present invention relates to a method for culturing a 3-dimensional lung cancer organoid and a method for preparing a patient-derived xenograft animal model using the same. More specifically, the present invention relates to a method for culturing a 3-dimensional lung cancer organoid, a lung cancer organoid prepared by the method, a medium composition for culturing the lung cancer organoid, a method for preparing a xenograft animal model using the lung cancer organoid, a patient-derived lung cancer organoid xenograft animal model prepared by the method, and a method for analyzing therapeutic efficacy of an anticancer agent and a method for screening an anticancer agent, using the animal model.

Abstract: An electronic device includes a display device, which may be fabricated using a described method. The display device includes a glass substrate including a first surface, a second surface opposite the first surface, and a side surface between the first surface and the second surface, an outermost structure on the first surface of the glass substrate and located adjacent to an edge of one side of the glass substrate, and a display area including a plurality of light emitting areas on the first surface of the glass substrate and located farther from the edge of the one side of the glass substrate than the outermost structure is. A minimum distance from the side surface of the glass substrate to the outermost structure is equal to 130 ?m or less.

Abstract: Provided are a resistance heated sapphire single crystal ingot grower, a method of manufacturing a resistance heated sapphire single crystal ingot, a sapphire single crystal ingot, and a sapphire wafer. The resistance heated sapphire single crystal ingot grower comprises according to an embodiment includes a chamber, a crucible included in the chamber and containing an alumina melt, and a resistance heating heater included inside the chamber and heating the crucible.

Abstract: Provided is a surface treatment method of a polishing pad. The surface treatment method of the polishing pad includes locating a wafer on the polishing pad including a polishing material, supplying a polishing pad polishing material between the polishing pad and the wafer to expose the polishing material included in the polishing pad, and polishing the wafer using the exposed polishing material.

Abstract: Provided are a resistance heated sapphire single crystal ingot grower, a method of manufacturing a resistance heated sapphire single crystal ingot, a sapphire single crystal ingot, and a sapphire wafer. The resistance heated sapphire single crystal ingot grower comprises according to an embodiment includes a chamber, a crucible included in the chamber and containing an alumina melt, and a resistance heating heater included inside the chamber and heating the crucible.

Abstract: By using a two-step RTP (rapid thermal processing) process, the wafer is provided which has an ideal semiconductor device region secured by controlling fine oxygen precipitates and OiSFs (Oxidation Induced Stacking Fault) located on the surface region of the wafer. By performing the disclosed two-step rapid thermal process, the distribution of defects can be accurately controlled and an ideal device active zone can be formed up to a certain distance from the surfaces of the wafer. In addition, it is possible to maximize the internal gettering (IG) efficiency by enabling the oxygen precipitates and the bulk stacking faults to have constant densities in the depth direction in an internal region of the wafer, that is, the bulk region. In order to obtain the constant concentration profile of the oxygen precipitates and the bulk stacking faults in the bulk region, the wafer is subjected to the aforementioned two-step rapid thermal process in a predetermined mixed gas atmosphere.

Abstract: By using a two-step RTP (rapid thermal processing) process, the wafer is provided which has an ideal semiconductor device region secured by controlling fine oxygen precipitates and OiSFs (Oxidation Induced Stacking Fault) located on the surface region of the wafer. By performing the disclosed two-step rapid thermal process, the distribution of defects can be accurately controlled and an ideal device active zone can be formed up to a certain distance from the surfaces of the wafer. In addition, it is possible to maximize the internal gettering (IG) efficiency by enabling the oxygen precipitates and the bulk stacking faults to have constant densities in the depth direction in an internal region of the wafer, that is, the bulk region. In order to obtain the constant concentration profile of the oxygen precipitates and the bulk stacking faults in the bulk region, the wafer is subjected to the aforementioned two-step rapid thermal process in a predetermined mixed gas atmosphere.

Abstract: By using a two-step RTP (rapid thermal processing) process, the wafer is provided which has an ideal semiconductor device region secured by controlling fine oxygen precipitates and OiSFs (Oxidation Induced Stacking Fault) located on the surface region of the wafer. By performing the disclosed two-step rapid thermal process, the distribution of defects can be accurately controlled and an ideal device active zone can be formed up to a certain distance from the surfaces of the wafer. In addition, it is possible to maximize the internal gettering (IG) efficiency by enabling the oxygen precipitates and the bulk stacking faults to have constant densities in the depth direction in an internal region of the wafer, that is, the bulk region. In order to obtain the constant concentration profile of the oxygen precipitates and the bulk stacking faults in the bulk region, the wafer is subjected to the aforementioned two-step rapid thermal process in a predetermined mixed gas atmosphere.

Abstract: A method of fabricating an annealed wafer of high quality by forming a defect-free active region of a device and controlling an irregular resistivity characteristic. The method includes a first annealing step of pre-heating a silicon wafer at a temperature of about 500° C. in a furnace in an ambience of a gas selected from the group consisting of Ar, N2 and an inert gas including Ar and N2; a second annealing step of changing the ambience of the gas into a 100% H2 gas ambience, increasing the temperature to 850° C.-1,150° C., and carrying out annealing for about an hour by maintaining the increased temperature; a third annealing step of changing the ambience of the gas into a 100% Ar gas ambience, increasing the temperature to about 1,200° C., and carrying out annealing for about an hour while the temperature of about 1,200° C. is maintained; and a temperature dropping step of decreasing the temperature in the furnace below about 500° C.

Abstract: An annealed wafer and manufacturing method thereof for producing a high quality annealed wafer free from slip defects despite high temperature annealing carried out on the silicon wafer to form a high density oxygen defect layer in the bulk of the silicon wafer as well as a denuded zone of a device active region by removing grown-in defects. The method invention includes the steps of preheating a silicon wafer loaded in an annealing furnace at a temperature of about 500° C., with the silicon wafer having an initial oxygen concentration of 11˜14 ppma; raising the temperature to at least 1,100° C. at a temperature rise rate of 1˜14° C./min by setting an ambience inside the annealing furnace as an inert gas including H2 or Ar, a mixed gas of H2 and Ar, or the like; maintaining the temperature of at least 1,100° C. for a predetermined time to carry out annealing; and dropping the temperature to about 500° C. at a temperature drop rate of 1˜14° C./min.

Abstract: A method of fabricating an annealed wafer of high quality by forming a defect-free active region of a device and controlling an irregular resistivity characteristic. The moethod includes a first annealing step of pre-heating a silicon wafer at a temperature of about 500° C. in a furnace in an ambience of a gas selected from the group consisting of Ar, N2 and an inert gas including Ar and N2; a second annealing step of changing the ambience of the gas into a 100% H2 gas ambience, increasing the temperature to 850° C.˜1,150° C., and carrying out annealing for about an hour by maintaining the increased temperature; a third annealing step of changing the ambience of the gas into a 100% Ar gas ambience, increasing the temperature to about 1,200° C., and carrying out annealing for about an hour while the temperature of about 1,200° C. is maintained; and a temperature dropping step of decreasing the temperature in the furnace below about 500° C.

Abstract: A method of fabricating a silicon wafer, which includes the steps of preparing a silicon wafer by slicing, grinding, and cleaning an ingot, inserting the silicon wafer in a diffusion furnace having an ambience of one of Ar, N2 and inert gas including Ar and N2, pre-heating and maintaining the diffusion furnace at about 500° C., changing the ambience into one of H2, Ar and inert gas including H2 and Ar successively, increasing a temperature of the diffusion furnace by a temperature-increasing speed of 50˜70° C./min between 500˜800° C., 10˜50° C./min between 800˜900° C., 0.5˜10° C./min between 900˜1000° C., and 0.1˜0.5° C./min between 1000˜1250° C., maintaining the diffusion furnace at 1200˜1250° C.

Abstract: A method of fabricating a silicon wafer, which includes the steps of preparing a silicon wafer by slicing, grinding, and cleaning an ingot, inserting the silicon wafer in a diffusion furnace having an ambience of one of Ar, N2 and inert gas including Ar and N2, pre-heating and maintaining the diffusion furnace at about 500° C., changing the ambience into one of H2, Ar and inert gas including H2 and Ar successively, increasing a temperature of the diffusion furnace by a temperature-increasing speed of 50˜70 ° C./min between 500˜800° C., 10˜50° C./min between 800˜900° C., 0.5˜10 ° C./min between 900˜1000° C., and 0.1˜0.5° C./min between 1000˜1250° C., maintaining the diffusion furnace at 1200˜1250° C.

Abstract: A method of treating a semiconductor wafer thermally and a semiconductor wafer fabricated thereby and, more particularly, a method of producing a wafer ideal for fabricating semiconductor devices thereon through thermal treatment. The method of removing defects contained in single crystalline semiconductor by treating the wafer thermally includes the steps of carrying out a first heat treatment on the wafer at a temperature equal to or higher than 1200° C., and carrying out a second heat treatment on the wafer at a temperature equal to or lower than 800° C.