Abstract: A catalyst for fuel cells and a method of manufacturing the catalyst are disclosed. The catalyst forms shells in a dense structure so as to prevent elution of a transition metal and increases dispersibility through hydrophilization of the surface of the catalyst so as to be uniformly dispersed when an ink for forming a fuel cell electrode is manufactured. The catalyst may thus increase the performance and durability of a fuel cell.

Abstract: Provided are a binder for an electrode, a negative electrode for a secondary battery including the binder, and a secondary battery, in which an active material layer is prevented from lifting from a negative electrode base material. A binder forming an electrode of a secondary battery includes a binder particle and a temperature-sensitive polymer grafted on a surface of the binder particle.

Abstract: Disclosed is fucosyllactose having antiviral activity and inhibitory activity against viral infection, and a method for preventing or treating a viral infection by administering a composition including fucosyllactose as an active ingredient to a subject in need thereof. It was found that 2?-fucosyllactose and 3-fucosyllactose, which are human milk oligosaccharides (HMOs), have antiviral activity, and in particular, 3-fucosyllactose in vitro and in vivo exhibits much higher antiviral activity and inhibitory activity against viral infection compared to 2?-fucosyllactose and is thus useful as an antiviral agent.

Abstract: An electronic device according to various embodiments of the present invention may comprise: a housing comprising a first surface facing in a first direction and a second surface facing in a second direction that is opposite to the first direction, the first surface comprising an at least partially transparent part and at least one opening formed adjacent to the at least partially transparent part; a camera positioned inside the housing, the camera comprising an image sensor facing in the first direction through the at least partially transparent part of the housing; and an acoustic component arranged between the first surface and the second surface, the acoustic component comprising a vibration plate configured to generate a sound such that the same moves in at least one direction selected from the first and second directions, a first passage formed in a third direction that is substantially perpendicular to the first direction such that the generated sound passes through the same, and a second passage forme

Abstract: A protective case configured to cover a portable electronic device is provided. The protective case may include a first card storage configured to receive a first card, and a second card storage configured to store a second card where the second card storage is spaced apart from the first card storage.

Abstract: A display device comprising: first and second pixels; a first data line connected to the first pixel and configured to have data voltages applied thereto; and a second data line connected to the second pixel, the second data line being adjacent to the first data line, and configured to have the data voltages applied thereto, wherein the first data line includes a 1A-th data line which is in a first data layer, and the second data line includes a 2B-th data line which is in a second data layer different from the first data layer.

Abstract: The present invention relates to electrode slurry coating apparatus and method, the present invention ultimately allowing the process efficiency to be increased and rate of errors to be reduced when double-layer structured active material layers are formed by temporally adjusting the height of first and second discharge outlets through which active material is discharged.

Abstract: A variable resistive memory device may include a semiconductor substrate, a device layer, an upper metal interconnect, a plurality of memory cells, and an uppermost metal interconnect. The device layer may be formed on the semiconductor substrate including memory cell array regions, and may include a plurality of lower metal interconnect layers. The upper metal interconnect may be arranged on the device layer, and may include a plurality of metal patterns. The plurality of memory may be arranged over the device layer in which the upper metal interconnect is formed and are in contact with certain metal patterns selected from the metal patterns constituting the upper metal interconnect. The uppermost metal interconnect may be located over the plurality of memory cells, and may be in contact with other portion of the metal patterns constituting the upper metal interconnect.

Abstract: A variable resistive memory device may include a semiconductor substrate, a device layer, an upper metal interconnect, a plurality of memory cells, and an uppermost metal interconnect. The device layer may be formed on the semiconductor substrate including memory cell array regions, and may include a plurality of lower metal interconnect layers. The upper metal interconnect may be arranged on the device layer, and may include a plurality of metal patterns. The plurality of memory may be arranged over the device layer in which the upper metal interconnect is formed and are in contact with certain metal patterns selected from the metal patterns constituting the upper metal interconnect. The uppermost metal interconnect may be located over the plurality of memory cells, and may be in contact with other portion of the metal patterns constituting the upper metal interconnect.

Abstract: A semiconductor device includes a signal transmission line extending in a first direction; an outer protective line extending in a substantially identical direction as the first direction and spaced apart from the signal transmission line by a predetermined distance along a second direction which is substantially perpendicular to the first direction; and an inner protective line, disposed between the outer protective line and the signal transmission line, and intermittently extending substantially in parallel with said signal transmission line and outer protective line.

Abstract: A semiconductor integrated circuit device may include a first signal line, a second signal line, a variable resistance material layer, and a third signal line. The second signal line may be positioned coplanar with the first signal line. The second signal line may be parallel to the first signal line. The variable resistance material layer may include a horizontal region arranged on the first and second signal lines, and may include a vertical region extending upwardly from an end of the horizontal region. The third signal line may be positioned on a plane different from a plane on which the first and second signal lines may be positioned. The third signal line may be arranged on an end of the vertical region of the variable resistance material layer.

Abstract: A semiconductor device includes a signal transmission line extending in a first direction; an outer protective line extending in a substantially identical direction as the first direction and spaced apart from the signal transmission line by a predetermined distance along a second direction which is substantially perpendicular to the first direction; and an inner protective line, disposed between the outer protective line and the signal transmission line, and intermittently extending substantially in parallel with said signal transmission line and outer protective line.

Abstract: A semiconductor device including power TSVs for stably supplying a power source is described. A semiconductor device includes a chip power pad placed in a first region of a chip, power through silicon vias (TSVs) connected to the chip power pad and placed in the second region of each of the chips, and metal lines configured to couple the chip power pad and the power TSVs.

Abstract: A semiconductor device including power TSVs for stably supplying a power source is described. A semiconductor device includes a chip power pad placed in a first region of a chip, power through silicon vias (TSVs) connected to the chip power pad and placed in the second region of each of the chips, and metal lines configured to couple the chip power pad and the power TSVs.

Abstract: Provided is a semiconductor apparatus in which a plurality of semiconductor chips stacked in a vertical direction. Each of the semiconductor chips comprises: a bank area comprising a plurality of banks configured to store data; and a peripheral area including a pad area in which a plurality of pads configured to receive signals for controlling the bank area and a plurality of TSV for electrically connecting the plurality of pads, respectively.

Abstract: Provided is a semiconductor apparatus in which a plurality of semiconductor chips stacked in a vertical direction. Each of the semiconductor chips comprises: a bank area comprising a plurality of banks configured to store data; and a peripheral area including a pad area in which a plurality of pads configured to receive signals for controlling the bank area and a plurality of TSV for electrically connecting the plurality of pads, respectively.

Abstract: A semiconductor device including power TSVs for stably supplying a power source is described. A semiconductor device includes a chip power pad placed in a first region of a chip, power through silicon vias (TSVs) connected to the chip power pad and placed in the second region of each of the chips, and metal lines configured to couple the chip power pad and the power TSVs.

Abstract: A semiconductor integrated circuit includes first power supply through-chip vias formed through the semiconductor chip to be in a line in a first direction of the semiconductor chip, second power supply through-chip vias formed through the semiconductor chip to be in, first power lines arranged in a second direction, wherein each of the plurality of first power lines is coupled to each of the first power supply through-chip vias, and second power lines arranged in the second direction, wherein each of the plurality of second power lines is coupled to each of the second power supply through-chip vias.

Abstract: Provided is a semiconductor integrated circuit. The semiconductor integrated circuit comprises: a pair of interconnections; a fuse connecting the pair of interconnections; and one or more heat dissipation patterns connecting the pair of interconnections and are disposed around the fuse.

Abstract: A gate in a semiconductor device is formed to have a dummy gate pattern that protects a gate. Metal lines are formed to supply power for a semiconductor device and transfer a signal. A semiconductor device includes a quad coupled receiver type input/output buffer. The semiconductor device is formed with a gate line that extends over an active region, and a gate pad located outside of the active region. The gate line and the gate pad are adjoined such that the gate line and a side of the gate pad form a line. Dummy gates may also be applied. The semiconductor device includes a first metal line patterns supplying power to a block having a plurality of cells, a second metal line pattern transferring a signal to the cells, and dummy metal line patterns divided into in a longitudinal direction.