Abstract: A method of analyzing power noise in a semiconductor device includes; generating modified current information by modifying present current information based on a previous analysis result, updating a current vector based on the modified current information, and generating a present analysis result by calculating a voltage vector from the updated current vector.

Abstract: A circuit modeling system includes a store a first net list. The first net list includes a plurality of semiconductor devices, a first power distribution network (PDN) connected to the plurality of semiconductor devices, and a signal network connected to the plurality of semiconductor devices that transmits signals to the plurality of semiconductor devices. A circuit simulation unit is configured to identify first semiconductor devices and second semiconductor devices from among the plurality of semiconductor devices. The first semiconductor devices are activated by receiving a signal through the signal network, and the second semiconductor devices are inactive. The circuit simulation unit is configured to reduce the first PDN to a second PDN based on the identified first semiconductor devices, and to generate a second net list including the signal network, the second PDN, and the first semiconductor devices.

Abstract: A method of analyzing power noise in a semiconductor device includes; generating modified current information by modifying present current information based on a previous analysis result, updating a current vector based on the modified current information, and generating a present analysis result by calculating a voltage vector from the updated current vector.

Abstract: A method of analyzing power noise in a semiconductor device includes; generating modified current information by modifying present current information based on a previous analysis result, updating a current vector based on the modified current information, and generating a present analysis result by calculating a voltage vector from the updated current vector.

Abstract: A system for designing a semiconductor package using a computing system, comprising: a virtual stacking module configured to receive a layout parameter for a first chip, a layout parameter for a second chip, and a layout parameter for a package substrate, and in response to the layout parameters of the first chip, the second chip, and the package substrate, generate a plurality of virtual layouts in which the first and second chips are stacked, on the package substrate; a modeling module configured to model operating parameters for the first and second chips and the package substrate in response to the virtual layouts; and a characteristic analyzing module configured to analyze operating characteristics of the virtual layouts in response to the modeled operating parameters.

Abstract: A method of analyzing power noise in a semiconductor device includes; generating modified current information by modifying present current information based on a previous analysis result, updating a current vector based on the modified current information, and generating a present analysis result by calculating a voltage vector from the updated current vector.

Abstract: A circuit modeling system includes a store a first net list. The first net list includes a plurality of semiconductor devices, a first power distribution network (PDN) connected to the plurality of semiconductor devices, and a signal network connected to the plurality of semiconductor devices that transmits signals to the plurality of semiconductor devices. A circuit simulation unit is configured to identify first semiconductor devices and second semiconductor devices from among the plurality of semiconductor devices. The first semiconductor devices are activated by receiving a signal through the signal network, and the second semiconductor devices are inactive. The circuit simulation unit is configured to reduce the first PDN to a second PDN based on the identified first semiconductor devices, and to generate a second net list including the signal network, the second PDN, and the first semiconductor devices.

Abstract: A three-dimensional semiconductor package and method for making the same include providing a first package layout parameter for a plurality of first terminals included in a first package, a second package layout parameter for a plurality of second terminals included in a second package disposed above or below the first package, and a connection terminal layout parameter for a plurality of connection terminals electrically connecting the first package and the second package; providing a first wiring connection layout between the first and second terminals and the connection terminals by applying a first process to the first package, second package, and connection terminal layout parameters; and providing a second wiring connection layout between the first and second terminals and the connection terminals by applying a second process, which is different from the first process, to the first wiring connection layout.

Abstract: A three-dimensional semiconductor package and method for making the same include providing a first package layout parameter for a plurality of first terminals included in a first package, a second package layout parameter for a plurality of second terminals included in a second package disposed above or below the first package, and a connection terminal layout parameter for a plurality of connection terminals electrically connecting the first package and the second package; providing a first wiring connection layout between the first and second terminals and the connection terminals by applying a first process to the first package, second package, and connection terminal layout parameters; and providing a second wiring connection layout between the first and second terminals and the connection terminals by applying a second process, which is different from the first process, to the first wiring connection layout.

Abstract: A system for designing a semiconductor package using a computing system, comprising: a virtual stacking module configured to receive a layout parameter for a first chip, a layout parameter for a second chip, and a layout parameter for a package substrate, and in response to the layout parameters of the first chip, the second chip, and the package substrate, generate a plurality of virtual layouts in which the first and second chips are stacked, on the package substrate; a modeling module configured to model operating parameters for the first and second chips and the package substrate in response to the virtual layouts; and a characteristic analyzing module configured to analyze operating characteristics of the virtual layouts in response to the modeled operating parameters.

Abstract: A power distribution network simulation method capable of speedily and accurately analyzing a large power distribution network. In the power distribution network simulation method, the large original circuit is reduced to a suitable size by using a variable reduction method, a solution of an equation of the reduced circuit is obtained, and a solution of an equation of the original circuit is restored based on the solution of the equation of the reduced circuit by using the variable reduction method. According to the power distribution network simulation method using the variable reduction method, it is possible to speedily and accurately analyze the large power distribution network.

Abstract: A power distribution network simulation method capable of speedily and accurately analyzing a large power distribution network. In the power distribution network simulation method, the large original circuit is reduced to a suitable size by using a variable reduction method, a solution of an equation of the reduced circuit is obtained, and a solution of an equation of the original circuit is restored based on the solution of the equation of the reduced circuit by using the variable reduction method. According to the power distribution network simulation method using the variable reduction method, it is possible to speedily and accurately analyze the large power distribution network.