Abstract: The present application relates to a method of generating a downlink frame. The method of generating the downlink frame includes: generating a first short sequence and a second short sequence indicating cell group information; generating a first scrambling sequence and a second scrambling sequence determined by the primary synchronization signal; generating a third scrambling sequence determined by the first short sequence and a fourth scrambling sequence determined by the second short sequence; scrambling the short sequences with the respective scrambling sequences; and mapping the secondary synchronization signal that includes the first short sequence scrambled with the first scrambling sequence, the second short sequence scrambled with the second scrambling sequence and the third scrambling sequence, the second short sequence scrambled with the first scrambling sequence and the first short sequence scrambled by the second scrambling sequence and the fourth scrambling sequence to a frequency domain.

Abstract: The present invention relates to a VOC reduction system and a VOC reduction method that applies pulse type thermal energy to a catalyst to activate the catalyst and oxidizes and removes the VOC.

Abstract: A transmitter and a receiver are provided. The transmitter includes a processing unit configured to receive a clock signal and a data signal, set a value of a consecutive identical digit (CID) value related to the data signal and generate a modulation signal during a unit interval (UI) based on the data signal and the CID value, and a transmitter driver configured to output output signals having different voltage levels during the unit interval by receiving the modulation signal.

Abstract: A portable terminal is capable of large screen display and includes an apparatus for driving the same. The portable terminal includes a first display panel unit for displaying a first image, a second display panel unit for displaying a second image, a first and a second trajectory discs being positioned opposite each other at one side of the first display panel unit and formed with a plurality of trajectory grooves at one side thereof, and a folding slide door unit combined between the first display panel unit and the second display panel unit. The folding slide door unit is formed with guide protrusions respectively so as to be slidably inserted into the trajectory grooves of the first and the second trajectory discs at both lateral sides thereof, and includes a plurality of slide doors so as to be slidably folded along the trajectory grooves.

Abstract: A portable terminal has the dual display module structure in which a plurality of panels provided in the portable terminal are combined with clear conjunction to display a distortionless large screen display. The portable terminal includes a first display panel unit for displaying a first image, a second display panel unit for displaying a g the second display panel unit with the first display panel unit with supporting rotational shift, and a film connecting unit facing the hinge unit. A film is inserted in the connecting unit for connecting the first display panel unit with the second display panel unit electrically.

Abstract: An information search method and apparatus employ an Inverse Hidden Markov Model (IHMM) for stochastically searching for a reference information model among a plurality of predetermined reference information models obtained by training that best matches unknown information which is expressed by a Hidden Markov Model (HMM) chain. The method and apparatus find an optimal path in a HMM state lattice using a minimum unlikelihood score, rather than a maximum likelihood score, and using a Viterbi algorithm, to recognize unknown information, so that unnecessary computations are avoided. The method and apparatus can be used for finding the most likely path through a vocabulary network for a given utterance.

Abstract: A bus encoding/decoding apparatus and method for a low power digital signal processor (DSP), which uses a narrow data bus, is provided. The apparatus for encoding n bits of data of a data bus, includes a conditional inverting unit for inverting each of (n−1) lower bits of n data when the most significant bit of the n bits of data is 1, a storage unit for storing the last n bits of data which is output to the bus, and a first exclusive OR operating unit for performing a bitwise exclusive OR operation on the lower (n−1) bits or data, which has been inverted by the conditional inverting unit, and the lower (n−1) bits of the n data, which has been stored in the storage unit, wherein the most significant bit of the n bits of data and (n−1) bits of data, which is obtained as the result of the bitwise exclusive OR operation performed by the first exclusive OR operating unit, are output.

Abstract: An information search method and apparatus using an Inverse Hidden Markov Model (IHMM) are provided.

Abstract: A bus encoding/decoding apparatus and method for a low power digital signal processor (DSP), which uses a narrow data bus, is provided. The apparatus for encoding n bits of data of a data bus, includes a conditional inverting unit for inverting each of (n−1) lower bits of n data when the most significant bit of the n bits of data is 1, a storage unit for storing the last n bits of data which is output to the bus, and a first exclusive OR operating unit for performing a bitwise exclusive OR operation on the lower (n−1) bits or data, which has been inverted by the conditional inverting unit, and the lower (n−1) bits of the n data, which has been stored in the storage unit, wherein the most significant bit of the n bits of data and (n−1) bits of data, which is obtained as the result of the bitwise exclusive OR operation performed by the first exclusive OR operating unit, are output.

Abstract: There is provided a low power consuming operating device for digital signal processing, which analyses a digital signal to be operated, determines whether the digital signal is a frequently encountered specified signal, and outputs a previously calculated value when the digital signal is the specified signal.

Abstract: A digital signal processor includes an execution unit separated into an arithmetic unit, a multiplier unit, a logic unit, a shift unit and a log unit, to implement CCITT G721 ADPCM algorithm with a relatively small size, which reduces the system cost. Also, since the digital signal processor primarily takes into consideration of low power consumption, it is applicable to a mobile communication system. Also, the digital signal processor is capable of implementing easily other ADPCM rates and algorithms as well as the ADPCM algorithm by modifying only the program of an instruction ROM.

Abstract: A digital data recovering apparatus which includes an edge detector, a threshold comparator, a position address generator, a position memory, a maximum position detector, a new position generator and a recovered data detector. The digital data recovering apparatus ensures that the desired data and clock reference can be recovered by exactly synchronizing the input data on a communication path, including a noise and/or jitter component.