Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit, and a control logic circuit. The memory cell array includes a plurality of bank arrays, and each of the bank arrays includes dynamic memory cells. The control logic circuit generates a first control signal to control the I/O gating circuit and a second control signal to control the ECC engine, in response to an access address and a command. The control logic circuit controls the ECC engine to perform s-bit ECC encoding on a write data to be stored in a first page of at least one bank array, in response to a first command, and controls the ECC engine to perform t-bit ECC decoding on a first codeword read from the first page, in response to a second command.

Abstract: Memory devices are provided. A memory device includes a voltage generation circuit that includes an offset compensator configured to receive a reference voltage and an offset code and to link the offset code to the reference voltage. The voltage generation circuit includes a comparator configured to compare the reference voltage linked to the offset code with a bit line pre-charge voltage and to output driving control signals. The voltage generation circuit includes a driver configured to output the bit line pre-charge voltage at a target level of the reference voltage in response to the driving control signals. The voltage generation circuit includes a background calibration circuit configured to generate the offset code for performing control so that a target short current flows through an output node of the driver from which the bit line pre-charge voltage is output. Related methods of generating a bit line pre-charge voltage are also provided.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes bank arrays, each of the bank arrays includes a first sub array and a second sub array, and each of the first sub array and the second sub array includes a normal cell region to store data bits and a parity cell region to store parity bits. The ECC engine generates the parity bits and corrects error bit. The I/O gating circuit is connected between the ECC engine and the memory cell array. The control logic circuit controls the I/O gating circuit to perform column access to the normal cell region according to a multiple of a burst length and to perform column access to the parity cell region according to a non-multiple of the burst length partially.

Abstract: A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit, and a control logic circuit. The memory cell array includes a plurality of bank arrays, and each of the bank arrays includes dynamic memory cells. The control logic circuit generates a first control signal to control the I/O gating circuit and a second control signal to control the ECC engine, in response to an access address and a command. The control logic circuit controls the ECC engine to perform s-bit ECC encoding on a write data to be stored in a first page of at least one bank array, in response to a first command, and controls the ECC engine to perform t-bit ECC decoding on a first codeword read from the first page, in response to a second command.

Abstract: The present invention relates to a nanocomposite for detecting hydrogen sulfide; a method for preparing the same; a novel reactive fluorogenic compound to be used in the method; a kit for detecting hydrogen sulfide comprising the nanocomposite; and a method for providing information for the diagnosis of a disease, which causes abnormal secretion of hydrogen sulfide, by using the nanocomposite.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes bank arrays, each of the bank arrays includes a first sub array and a second sub array, and each of the first sub array and the second sub array includes a normal cell region to store data bits and a parity cell region to store parity bits. The ECC engine generates the parity bits and corrects error bit. The I/O gating circuit is connected between the ECC engine and the memory cell array. The control logic circuit controls the I/O gating circuit to perform column access to the normal cell region according to a multiple of a burst length and to perform column access to the parity cell region according to a non-multiple of the burst length partially.

Abstract: A method for detecting biomaterial by means of a dye having a linear upconversion fluorescent property is provided. The method includes the steps of: i) preparing a fluorophore having a linear upconversion fluorescent property; ii) reacting the fluorophore and biomaterial to obtain a reaction complex thereof; iii) exciting the reaction complex by means of a light source having a longer wavelength than the maximum light-emitting wavelength of the fluorophore; and iv) detecting and measuring the light-emitting signal having a shorter wavelength than the wavelength of the excited light emitted from the excited reaction complex. A system and a kit for detecting biomaterial using a dye having a linear upconversion fluorescent property are also provided.

Abstract: A bit line sense amplifier with an enhanced sensing margin is provided. The bit line sense amplifier includes a sensing amplification circuit connected to a bit line and a complementary bit line and configured to sense a voltage change of the bit line and adjust voltages of a sensing bit line. Also provided is a complementary sensing bit line based on the sensed voltage change, wherein the sensing amplification circuit includes a first transistor connected between the complementary sensing bit line and a first high-voltage node and controlled by the voltage change of the bit line. A second transistor is connected between the sensing bit line and a second high-voltage node and controlled by a voltage change of the complementary bit line.

Abstract: A bit line sense amplifier with an enhanced sensing margin is provided. The bit line sense amplifier includes a sensing amplification circuit connected to a bit line and a complementary bit line and configured to sense a voltage change of the bit line and adjust voltages of a sensing bit line. Also provided is a complementary sensing bit line based on the sensed voltage change, wherein the sensing amplification circuit includes a first transistor connected between the complementary sensing bit line and a first high-voltage node and controlled by the voltage change of the bit line. A second transistor is connected between the sensing bit line and a second high-voltage node and controlled by a voltage change of the complementary bit line.

Abstract: An antifuse memory device includes an antifuse memory cell, a reference current generation unit, and a comparison unit. The antifuse memory cell includes an antifuse. The reference current generation unit provides a reference current selected from a plurality of reference currents. The comparison unit compares an intensity of a cell current flowing through the antifuse with an intensity of the reference current and provides an output signal corresponding to a result of the comparison.

Abstract: Provided is a bit line sense amplifier source node control circuit of a semiconductor memory device. The sense amplifier source node control circuit may include a source driver connected between a source node of a sense amplifier and a sense amplifier driving signal line, for driving the source node of the sense amplifier to a set voltage level. The sense amplifier source node control circuit may also include: a floating circuit for floating the sense amplifier driving signal line in a set operating mode; and a controller connected in parallel with the source driver between the source node of the sense amplifier and the sense amplifier driving signal line, for controlling a level of the sense amplifier driving signal line in the set operating mode.

Abstract: one example embodiment, a voltage regulator includes a regulating unit configured to generate a cell array operating voltage based on a power supply voltage and a reference voltage, a power switch control unit configured to generate a power switch control signal based on a sensing enable signal, and a power switch unit configured to compensate for a drop in the cell array operating voltage based on the power supply voltage and the power switch control signal, the cell array operating voltage dropping when the sensing enable signal is activated.

Abstract: Provided is a bit line sense amplifier source node control circuit of a semiconductor memory device. The sense amplifier source node control circuit may include a source driver connected between a source node of a sense amplifier and a sense amplifier driving signal line, for driving the source node of the sense amplifier to a set voltage level. The sense amplifier source node control circuit may also include: a floating circuit for floating the sense amplifier driving signal line in a set operating mode; and a controller connected in parallel with the source driver between the source node of the sense amplifier and the sense amplifier driving signal line, for controlling a level of the sense amplifier driving signal line in the set operating mode.

Abstract: An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

Abstract: An antifuse memory device includes an antifuse memory cell, a reference current generation unit, and a comparison unit. The antifuse memory cell includes an antifuse. The reference current generation unit provides a reference current selected from a plurality of reference currents. The comparison unit compares an intensity of a cell current flowing through the antifuse with an intensity of the reference current and provides an output signal corresponding to a result of the comparison.

Abstract: An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

Abstract: An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

Abstract: An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

Abstract: An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.