Patents by Inventor Younghwi Yang
Younghwi Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990189Abstract: A nonvolatile memory device includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings that are divided into a plurality of stacks disposed in the vertical direction, and each of the plurality of stacks includes at least one dummy word-line. The control circuit controls a program operation by applying a program voltage to a selected word-line of the plurality of cell strings during a program execution period and by reducing a voltage level of a dummy voltage applied to the at least one dummy word-line of at least one upper stack from among the plurality of stacks during the program execution period. The at least one upper stack is disposed at a higher position than a selected stack in the vertical direction and the selected stack from among the plurality of stacks includes the selected word-line.Type: GrantFiled: June 13, 2022Date of Patent: May 21, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Younghwi Yang, Joonsuc Jang
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Publication number: 20230207026Abstract: A nonvolatile memory device includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings that are divided into a plurality of stacks disposed in the vertical direction, and each of the plurality of stacks includes at least one dummy word-line. The control circuit controls a program operation by applying a program voltage to a selected word-line of the plurality of cell strings during a program execution period and by reducing a voltage level of a dummy voltage applied to the at least one dummy word-line of at least one upper stack from among the plurality of stacks during the program execution period. The at least one upper stack is disposed at a higher position than a selected stack in the vertical direction and the selected stack from among the plurality of stacks includes the selected word-line.Type: ApplicationFiled: June 13, 2022Publication date: June 29, 2023Inventors: YOUNGHWI YANG, JOONSUC JANG
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Patent number: 11475972Abstract: A controller includes control pins, a buffer memory, an error correction circuit, and a processor driving a read level search unit for a read operation of at least one non-volatile memory device, in which the read level search unit receives fail bit information of a sector error-corrected in the first page from the at least one non-volatile memory device when the error correction of the first read data is not possible, and searches for an optimal read level or set a soft decision offset using the fail bit information.Type: GrantFiled: July 6, 2021Date of Patent: October 18, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Younghwi Yang, Ilhan Park, Jinyoung Kim, Sehwan Park, Dongmin Shin
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Publication number: 20220180957Abstract: A controller includes control pins, a buffer memory, an error correction circuit, and a processor driving a read level search unit for a read operation of at least one non-volatile memory device, in which the read level search unit receives fail bit information of a sector error-corrected in the first page from the at least one non-volatile memory device when the error correction of the first read data is not possible, and searches for an optimal read level or set a soft decision offset using the fail bit information.Type: ApplicationFiled: July 6, 2021Publication date: June 9, 2022Inventors: Younghwi Yang, Ilhan Park, Jinyoung Kim, Sehwan Park, Dongmin Shin
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Patent number: 10037795Abstract: Systems and methods relate to a seven transistor static random-access memory (7T SRAM) bit cell which includes a first inverter having a first pull-up transistor, a first pull-down transistor, and a first storage node, and a second inverter having a second pull-up transistor, a second pull-down transistor, and a second storage node. The second storage node is coupled to gates of the first pull-up transistor and the first pull-down transistor. A transmission gate is configured to selectively couple the first storage node to gates of the second pull-up transistor and the second pull-down transistor during a write operation, a standby mode, and a hold mode, and selectively decouple the first storage node from gates of the first pull-up transistor and a first pull-down transistor during a read operation. The 7T SRAM bit cell can be read or written through an access transistor coupled to the first storage node.Type: GrantFiled: September 27, 2014Date of Patent: July 31, 2018Assignees: QUALCOMM Incorporated, INDUSTRY-ACADEMIC COOPERATION FOUNDATIONInventors: Seong-Ook Jung, Younghwi Yang, Stanley Seungchul Song, Zhongze Wang, Choh Fei Yeap
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Patent number: 9583178Abstract: Methods and apparatuses for static memory cells. A static memory cell may include a first pass gate transistor including a first back gate node and a second pass gate transistor including a second back gate node. The static memory cell may include a first pull down transistor including a third back gate node and a second pull down transistor including a fourth back gate node. The source node of the first pull down transistor, source node of the second pull down transistor, and first, second, third, and fourth back gate nodes are electrically coupled to each other to form a common node.Type: GrantFiled: January 15, 2013Date of Patent: February 28, 2017Assignees: QUALCOMM Incorporated, Industry-Academic Cooperation Foundation Yonsei UniversityInventors: Seong-Ook Jung, Younghwi Yang, Bin Yang, Choh Fei Yeap
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Patent number: 9460777Abstract: A device includes a static random access memory (SRAM) cell and a read buffer coupled to an output of the SRAM cell. The read buffer includes an inverter and a switch. An input of the inverter is responsive to the output of the SRAM cell. A control terminal of the switch is responsive to an output of the inverter.Type: GrantFiled: August 2, 2013Date of Patent: October 4, 2016Assignees: Qualcomm Incorporated, Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seong-Ook Jung, Younghwi Yang, Stanley Seungchul Song, Zhongze Wang, Choh fei Yeap
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Patent number: 9336863Abstract: A static random-access memory (SRAM) memory cell includes a pair of cross-coupled inverters and a gating transistor coupled to a first node of a first inverter of the pair of cross-coupled inverters. A gate of the gating transistor is coupled to a first wordline. The gating transistor is configured to selectively couple a bitline to the first node of the first inverter responsive to a first wordline signal. The first inverter has a second node coupled to a second wordline. The first wordline and the second wordline are each independently controllable.Type: GrantFiled: June 30, 2014Date of Patent: May 10, 2016Assignee: QUALCOMM IncorporatedInventors: Seong-Ook Jung, Younghwi Yang, Stanley Seungchul Song, Choh Fei Yeap, Zhongze Wang
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Publication number: 20160093364Abstract: Systems and methods include a static random-access memory (SRAM) bit cell circuit having an access transistor configured to pass a read current to a storage node, the access transistor including an access transistor back gate. The access transistor back gate is biased to enable selective current boosting of the read current during a read operation.Type: ApplicationFiled: September 27, 2014Publication date: March 31, 2016Inventors: Seong-Ook JUNG, Younghwi YANG, Stanley Seungchul SONG, Zhongze WANG, Choh Fei YEAP
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Publication number: 20150380080Abstract: A static random-access memory (SRAM) memory cell includes a pair of cross-coupled inverters and a gating transistor coupled to a first node of a first inverter of the pair of cross-coupled inverters. A gate of the gating transistor is coupled to a first wordline. The gating transistor is configured to selectively couple a bitline to the first node of the first inverter responsive to a first wordline signal. The first inverter has a second node coupled to a second wordline. The first wordline and the second wordline are each independently controllable.Type: ApplicationFiled: June 30, 2014Publication date: December 31, 2015Inventors: Seong-Ook Jung, Younghwi Yang, Stanley Seungchul Song, Choh Fei Yeap, Zhongze Wang
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Patent number: 9111635Abstract: Static random access memories (SRAM) with read-preferred cell structures and write drivers are disclosed. In one embodiment, the SRAM has a six transistor bit cell. The read-preferred bit cell is implemented by providing two inverters, each having a pull up transistor, a pull down transistor and a pass gate transistor. Each pull up transistor is associated with a feedback loop. The feedback loop improves random static noise margin. Each transistor has a width and a length. The lengths of the pass gate transistors are increased. The widths of the pull down transistors are equal to one another and also equal to the widths of the pass gate transistors. The widths of the pass gate and pull down transistors may also be increased relative to prior designs. A write assist circuit may also be used to improve performance.Type: GrantFiled: April 24, 2013Date of Patent: August 18, 2015Assignee: QUALCOMM IncorporatedInventors: Seong-Ook Jung, Younghwi Yang, Bin Yang, Zhongze Wang, Choh fei Yeap
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Publication number: 20150036417Abstract: A device includes a static random access memory (SRAM) cell and a read buffer coupled to an output of the SRAM cell. The read buffer includes an inverter and a switch. An input of the inverter is responsive to the output of the SRAM cell. A control terminal of the switch is responsive to an output of the inverter.Type: ApplicationFiled: August 2, 2013Publication date: February 5, 2015Applicant: Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seong-Ook Jung, Younghwi Yang, Stanley Seungchul Song, Zhongze Wang, Choh fei Yeap
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Publication number: 20140211546Abstract: Static random access memories (SRAM) with read-preferred cell structures and write drivers are disclosed. In one embodiment, the SRAM has a six transistor bit cell. The read-preferred bit cell is implemented by providing two inverters, each having a pull up transistor, a pull down transistor and a pass gate transistor. Each pull up transistor is associated with a feedback loop. The feedback loop improves random static noise margin. Each transistor has a width and a length. The lengths of the pass gate transistors are increased. The widths of the pull down transistors are equal to one another and also equal to the widths of the pass gate transistors. The widths of the pass gate and pull down transistors may also be increased relative to prior designs. A write assist circuit may also be used to improve performance.Type: ApplicationFiled: April 24, 2013Publication date: July 31, 2014Applicant: Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seong-Ook Jung, Younghwi Yang, Bin Yang, Zhongze Wang, Choh fei Yeap
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Publication number: 20140036578Abstract: Methods and apparatuses for static memory cells. A static memory cell may include a first pass gate transistor including a first back gate node and a second pass gate transistor including a second back gate node. The static memory cell may include a first pull down transistor including a third back gate node and a second pull down transistor including a fourth back gate node. The source node of the first pull down transistor, source node of the second pull down transistor, and first, second, third, and fourth back gate nodes are electrically coupled to each other to form a common node.Type: ApplicationFiled: January 15, 2013Publication date: February 6, 2014Applicant: QUALCOMM IncorporatedInventors: Seong-Ook Jung, Younghwi Yang, Bin Yang, Choh Fei Yeap