Patents by Inventor Young In Jhon

Young In Jhon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10804674
    Abstract: Provided are a saturable absorber including at least one material selected from a group of MXenes, and a Q-switching and mode-locked pulsed laser system using the same.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: October 13, 2020
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Young Min Jhon, Young In Jhon, Byunghyuck Moon, Minah Seo, Taikjin Lee, Jae Hun Kim, Young Tae Byun, Seok Lee
  • Patent number: 10753804
    Abstract: The present invention relates to a terahertz (THz) wave detecting sensor including a MXene material represented by the following Formula 1 as a sensing material: M(n+1)Xn,??[Formula 1] wherein, in Formula 1, M is at least one transition metal selected from early transition metal elements, X is at least one selected from C and N, and n is an integer selected from 1 to 3.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: August 25, 2020
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Young Min Jhon, Minah Seo, Young In Jhon
  • Publication number: 20200158576
    Abstract: The present invention relates to a terahertz (THz) wave detecting sensor including a MXene material represented by the following Formula 1 as a sensing material: M(n+1)Xn,??[Formula 1] wherein, in Formula 1, M is at least one transition metal selected from early transition metal elements, X is at least one selected from C and N, and n is an integer selected from 1 to 3.
    Type: Application
    Filed: March 5, 2019
    Publication date: May 21, 2020
    Inventors: Young Min JHON, Minah SEO, Young In JHON
  • Patent number: 10401320
    Abstract: Provided are a method of fabricating a 3-dimensional transistor sensor and the sensor and a sensor array thereof. The method of fabricating the 3-dimensional transistor sensor includes forming an insulating layer on a silicon substrate, forming a silicon layer on the insulating layer and forming a 3-dimensional silicon fin by etching the silicon layer, forming a source area and a source electrode at one end of the silicon fin, forming a drain area and a drain electrode at the other end the silicon fin, and forming a gate area at a center of the silicon fin, surrounding three surfaces of a gate with a gate insulating layer, forming a sensing gate layer configured to surround a portion of the gate insulating layer, and sealing an upper portion of the gate insulating layer excluding the sensing gate layer.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: September 3, 2019
    Assignee: Korea Institute of Science and Technology
    Inventors: Young In Jhon, Young Tae Byun, Yong Tae Kim, Young Min Jhon
  • Patent number: 10245557
    Abstract: One aspect of the disclosed is to provide a method of manufacturing a nanoporous multilayer graphene membrane, including a first step of oxidizing a surface of a multilayer graphene membrane, a second step of reducing the oxidized surface of the multilayer graphene to carry out reductive etching such that oxidized carbon atoms on the surface are naturally and randomly dispersed, and a third step of repeatedly performing a series of the first and the second steps until nanopores penetrating the multilayer graphene are formed.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: April 2, 2019
    Assignee: Korea Institute of Science and Technology
    Inventors: Young Min Jhon, Young In Jhon, Seok Lee
  • Publication number: 20190072516
    Abstract: Provided are a method of fabricating a 3-dimensional transistor sensor and the sensor and a sensor array thereof. The method of fabricating the 3-dimensional transistor sensor includes forming an insulating layer on a silicon substrate, forming a silicon layer on the insulating layer and forming a 3-dimensional silicon fin by etching the silicon layer, forming a source area and a source electrode at one end of the silicon fin, forming a drain area and a drain electrode at the other end the silicon fin, and forming a gate area at a center of the silicon fin, surrounding three surfaces of a gate with a gate insulating layer, forming a sensing gate layer configured to surround a portion of the gate insulating layer, and sealing an upper portion of the gate insulating layer excluding the sensing gate layer.
    Type: Application
    Filed: March 29, 2018
    Publication date: March 7, 2019
    Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Young In JHON, Young Tae BYUN, Yong Tae Kim, Young Min JHON
  • Publication number: 20180147542
    Abstract: One aspect of the disclosed is to provide a method of manufacturing a nanoporous multilayer graphene membrane, including a first step of oxidizing a surface of a multilayer graphene membrane, a second step of reducing the oxidized surface of the multilayer graphene to carry out reductive etching such that oxidized carbon atoms on the surface are naturally and randomly dispersed, and a third step of repeatedly performing a series of the first and the second steps until nanopores penetrating the multilayer graphene are formed.
    Type: Application
    Filed: November 24, 2017
    Publication date: May 31, 2018
    Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Young Min JHON, Young In JHON, Seok LEE
  • Publication number: 20180102624
    Abstract: Provided are a saturable absorber including at least one material selected from a group of MXenes, and a Q-switching and mode-locked pulsed laser system using the same.
    Type: Application
    Filed: October 6, 2017
    Publication date: April 12, 2018
    Inventors: Young Min Jhon, Young In Jhon, BYUNGHYUCK MOON, MINAH SEO, Taikjin Lee, JAE HUN KIM, Young Tae Byun, Seok Lee
  • Publication number: 20060158716
    Abstract: The present invention relates to an apparatus and a method for realizing all-optical NOR logic device using the gain saturation characteristics of a semiconductor optical amplifier (SOA). More particularly, the invention relates to a 10 Gbit/s all-optical NOR logic device among all-optical logic devices, in which a signal transmitted from a given point of an optical circuit such as an optical computing circuit is used as a pump signal and a probe signal.
    Type: Application
    Filed: January 20, 2005
    Publication date: July 20, 2006
    Applicant: Korea Institute of Science and Technology
    Inventors: Young Byun, Jae Kim, Young Jhon, Seok Lee, Deok Woo, Sun Kim, Jong Yi