Patents by Inventor Young-Jae Jung

Young-Jae Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7176139
    Abstract: Disclosed is an etching method for semiconductor processing by which a pattern loading phenomenon is reduced. First, plasma is generated while setting a bias power applied to a wafer to zero and applying a source power. After a predetermined time period, an etching process is implemented onto a predetermined layer formed on the wafer by setting the bias power to a predetermined value. Since by-products generated during preceding etching processes can be readily removed during an etching using plasma, an etching process change due to a difference of pattern densities can be reduced. In addition, a progressive pattern loading generated as the number of processed wafers increase, can be prevented.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: February 13, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-Jae Jung
  • Publication number: 20070023916
    Abstract: The semiconductor structure includes an etch target layer to be pattemed, a multiple bottom anti-reflective coating (BARC) layer, and a photoresist (PR) pattern. The multiple BARC layer includes a first mask layer formed on the etch target layer and containing carbon, and a second mask layer formed on the first mask layer and containing silicon. A PR layer formed on the multiple BARC layer undergoes photolithography to form the PR pattern on the multiple BARC layer. The multiple BARC layer has a reflectance of 2% or less, and an interface angle between the PR pattern and the multiple BARC layer is 80° to 90°.
    Type: Application
    Filed: July 28, 2006
    Publication date: February 1, 2007
    Inventors: Jung-hwan Hah, Yun-sook Chae, Han-ku Cho, Chang-jin Kang, Sang-gyun Woo, Man-hyoung Ryoo, Young-jae Jung
  • Publication number: 20070000869
    Abstract: Disclosed is an etching method for semiconductor processing by which a pattern loading phenomenon is reduced. First, plasma is generated while setting a bias power applied to a wafer to zero and applying a source power. After a predetermined time period, an etching process is implemented onto a predetermined layer formed on the wafer by setting the bias power to a predetermined value. Since by-products generated during preceding etching processes can be readily removed during an etching using plasma, an etching process change due to a difference of pattern densities can be reduced. In addition, a progressive pattern loading generated as the number of processed wafers increase, can be prevented.
    Type: Application
    Filed: September 8, 2006
    Publication date: January 4, 2007
    Inventor: Young-Jae Jung
  • Publication number: 20070000610
    Abstract: Disclosed is an etching method for semiconductor processing by which a pattern loading phenomenon is reduced. First, plasma is generated while setting a bias power applied to a wafer to zero and applying a source power. After a predetermined time period, an etching process is implemented onto a predetermined layer formed on the wafer by setting the bias power to a predetermined value. Since by-products generated during preceding etching processes can be readily removed during an etching using plasma, an etching process change due to a difference of pattern densities can be reduced. In addition, a progressive pattern loading generated as the number of processed wafers increase, can be prevented.
    Type: Application
    Filed: September 8, 2006
    Publication date: January 4, 2007
    Inventor: Young-Jae Jung
  • Publication number: 20040047713
    Abstract: Disclosed is a screwed nail including a nail body having a shank, and a head formed at one end of the shank, the shank having a tip at the other end thereof, wherein the shank has threaded portions respectively formed at opposite sides of a middle portion of the shank, the threaded portions having threads with opposite angles of threading, respectively. It is possible to achieve easy driving of the screwed nail while providing a high fastening force by forming the threaded portions to have opposite angles of threading, and appropriately adjusting those angles of threading, and respective diameters of the threaded portions.
    Type: Application
    Filed: September 9, 2002
    Publication date: March 11, 2004
    Inventor: Young Jae Jung
  • Publication number: 20040043612
    Abstract: Disclosed is an etching method for semiconductor processing by which a pattern loading phenomenon is reduced. First, plasma is generated while setting a bias power applied to a wafer to zero and applying a source power. After a predetermined time period, an etching process is implemented onto a predetermined layer formed on the wafer by setting the bias power to a predetermined value. Since by-products generated during preceding etching processes can be readily removed during an etching using plasma, an etching process change due to a difference of pattern densities can be reduced. In addition, a progressive pattern loading generated as the number of processed wafers increase, can be prevented.
    Type: Application
    Filed: April 30, 2003
    Publication date: March 4, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Young-Jae Jung