Patents by Inventor Young-Jun Moon

Young-Jun Moon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120043116
    Abstract: Disclosed herein are printed circuit board assemblies made of a brittle material such as silicon, glass or ceramic and provided with a connector to electrically connect the same to an external connection member, and a method for molding the printed circuit board assembly wherein the printed circuit board assembly is molded by applying a polymer resin thereto to impart hardness to the printed circuit board assembly, and an electrode terminal to connect the same to the external connection member is exposed to the outside. Disclosed herein is also an interconnection structure of an interposer, the interconnection structure electrically connected to a main printed circuit board (PCB) through a solder joint is interposed between the interposer and the solder joint to prevent or reduce concentration of stress on the solder joint caused by differences in coefficients thermal expansion between the interposer and the main PCB.
    Type: Application
    Filed: August 17, 2011
    Publication date: February 23, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun Tae Kim, Tae Sang Park, Young Jun Moon, Soon Min Hong
  • Publication number: 20120018084
    Abstract: Disclosed herein is a printed circuit board assembly manufacturing device and method of manufacturing a printed circuit board assembly. The printed circuit board assembly manufacturing device may include a fusing unit configured to cure a conductive adhesive used to fix electronic components having different heights to a printed circuit board. The fusing unit may be configured to cure the conductive adhesive while simultaneously applying pressure to the electronic components having different heights.
    Type: Application
    Filed: July 6, 2011
    Publication date: January 26, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung Woon Jang, Seungbae Park, Young Jun Moon, Soon Min Hong, Chang-kyu Chung, Dae Jung Kim, Sang il Hong
  • Publication number: 20120018186
    Abstract: Disclosed herein is a case structure of an electronic product to which a film-type electronic circuit is adhered. The case structure may include a case of an electronic product and a first film adhered to the case. The case structure may further include a second film adhered to the first film such that one surface of the second film contacts the first film, and an electronic circuit layer adhered to the first film. The electronic circuit layer may be arranged between the first film and the second film, wherein the first film is thermally adhered to the case. The first film may have a melting at a melting point that is lower than a heat-resistant temperature of the case.
    Type: Application
    Filed: July 6, 2011
    Publication date: January 26, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ja Myeong Koo, Soon Min Hong, Tae Sang Park, Young Jun Moon, Gyun Heo, Sun Gu Yi
  • Publication number: 20110272181
    Abstract: According to an example embodiment, the multilayer stretchable cable includes a multilayer stretchable film and a plurality of conductive lines in the stretchable film. The conductive lines are in at least two different layers of the multilayer stretchable film in a thickness direction of the stretchable film, at least one conductive line is a signal line and at least one other conductive line in a layer adjacent to the signal line is a ground line. The signal line and the ground line are in zigzag patterns and are parallel to a width direction of the multilayer stretchable film.
    Type: Application
    Filed: April 1, 2011
    Publication date: November 10, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ja Myeong Koo, Soon Wan Chung, Soon Min Hong, Young Jun Moon
  • Publication number: 20110154661
    Abstract: Disclosed herein is a method for fabricating a printed circuit board assembly by adhering an element to a printed circuit board without using any solder. The printed circuit board may be fabricated by sequentially applying a conductor-containing first ink and an insulator-containing second ink onto a base substrate by ink-jet printing to form a printed circuit board, mounting an element on the printed circuit board such that an electrode of the element contacts a conductive layer and curing the conductive layer at a high temperature.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 30, 2011
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Min Young Park, Young Jun Moon, Hyun Joo Han, Gyun Heo, Kyung Woon Jang, Sang il Hong, Dong Seok Baek
  • Publication number: 20110026233
    Abstract: Disclosed herein is an apparatus for manufacturing an elastic cable including conductor tracks arranged in a zigzag shape between elastic films. The apparatus may include a conductor track supplying unit to supply at least one conductor track, an aligning unit to align the at least one conductor track supplied from the conductor track supplying unit, a film supplying unit to supply elastic films such that the at least one conductor track is surrounded by the elastic films, and a thermal lamination roller unit to thermally laminate the at least one conductor track arranged between the elastic films, wherein the aligning unit is reciprocally movable to arrange the at least one conductor track in a zigzag shape between the elastic films when the at least one conductor track is supplied to the thermal lamination roller unit.
    Type: Application
    Filed: June 28, 2010
    Publication date: February 3, 2011
    Inventors: Soon Min Hong, Ja Myeong Koo, Young Jun Moon, Sun Gu Yi
  • Publication number: 20100243309
    Abstract: Disclosed is a connection structure for a circuit board using a solder bump to arrange circuit boards. The circuit board connection structure includes a solder bump prepared on one of two circuit boards and a perforated part formed at the other of the circuit boards to receive the solder bump. Facing both circuit boards towards each other and inserting the solder bump into the perforated part, the circuit boards are desirably arranged.
    Type: Application
    Filed: March 12, 2010
    Publication date: September 30, 2010
    Inventors: Hyun Tae Kim, Tae Sang Park, Young Jun Moon, Soon Min Hong, Hyo Young Shin
  • Publication number: 20100248505
    Abstract: Disclosed herein is a printed circuit board and a connecting method thereof. The connecting method of the circuit board assembly may include molding the printed circuit board assembly by applying a resin to the printed circuit board assembly, exposing ends of the electrode terminals of a connector mounted on a printed circuit board by partially removing the molded printed circuit board assembly, and connecting a connection member to the exposed ends of the electrode terminals of the connector. Therefore, even if the whole of the printed circuit board assembly is molded, the connection member may be freely connected to the connector of the printed circuit board assembly.
    Type: Application
    Filed: March 15, 2010
    Publication date: September 30, 2010
    Inventors: Hyun Tae Kim, Tae Sang Park, Young Jun Moon, Soon Min Hong, Hyo Young Shin
  • Patent number: 7755181
    Abstract: An IC package including a plurality of BGA IC packages stacked on a printed circuit board and a method of manufacturing the same. The IC package includes a printed circuit board, a first BGA IC package, having a plurality of first solder balls, stacked on the printed circuit board, a second BGA IC package, having a plurality of second solder balls, stacked on the first BGA IC package, and an interposer having a plurality of through-holes, which are filled by the second solder balls in a molten state such that the length of the second solder balls increases while the second solder balls harden, the interposer being joined to the top of the first BGA IC package.
    Type: Grant
    Filed: October 16, 2007
    Date of Patent: July 13, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun Joo Han, Tae Sang Park, Se Yeong Jang, Young Jun Moon, Jung Hyeon Kim, Sung Wook Kang
  • Publication number: 20090139758
    Abstract: A printed circuit board (PCB) assembly is disclosed, which includes a first PCB on which a plurality of first electrode terminals are arranged at intervals from one another; a second PCB on which a plurality of second electrode terminals respectively connected with the first electrode terminals are arranged at intervals from one another; and separation preventing member which prevents the first and the second electrode terminals from deviating from their correct positions when the first and the second electrode terminals are ultrasonically-welded to each other. Accordingly, lateral movement of the first and the second PCBs relative to each other is restricted owing to the separation preventing member, the plurality of first electrode terminals and second electrode terminals can be bonded to each other without deviating from their correct positions.
    Type: Application
    Filed: June 3, 2008
    Publication date: June 4, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyo Young Shin, Seung Boo Jung, Young Jun Moon, Soon Min Hong, Chang Yong Lee, Ja Myeong Koo, Hyun Tae Kim, Jong Bum Lee, Hyun Joo Han
  • Publication number: 20090059498
    Abstract: An electronic appliance to achieve an increased rigidity thereof with a simplified manner without any change in design and configuration and a method for manufacturing the same. The electronic appliance includes a case defining the outer appearance of the electronic appliance, and a printed circuit board disposed in the case and having electronic elements mounted thereon. A resin is filled between the case and the printed circuit board.
    Type: Application
    Filed: June 9, 2008
    Publication date: March 5, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeo Woo Jeong, Tae Sang Park, Young Jun Moon, Hark Byeong Park
  • Patent number: 7486091
    Abstract: A test unit usable with a board having, an electronic component includes at least one testing point provided in each electronic component to test electric properties and a connection state of the plurality of electronic components connected to the board. The test unit usable with a PCB having the electronic component includes a testing point formed on the electronic component, thereby an enhancing high integration of the board.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: February 3, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-sang Park, Jung-soon Kim, Young-jun Moon, Jun-young Lee
  • Patent number: 7449907
    Abstract: A test unit to test a board having an area array package mounted therein includes the board, the area array package having an electronic component, a plurality of package pins including a plurality of contact pins connected with the electronic component and a plurality of no-contact pins not connected with the electronic component, and a plurality of contact members respectively provided on the plurality of contact pins and the plurality of no-contact pins to connect the plurality of package pins with the board, a plurality of board contact parts provided on the board and connected with the plurality of contact members to be connected with the plurality of package pins, at least one first connection part provided in the area array package to electrically connect the plurality of no-contact pins with each other in pairs, at least one second connection part provided on the board to electrically connect the plurality of board contact parts with each other in pairs to form a circuit line arranged alternately with
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: November 11, 2008
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Se-young Jang, Masaharu Tsukue, Young-jun Moon
  • Publication number: 20080198567
    Abstract: Disclosed is a multilayer printed circuit board. The multilayer printed circuit board includes a power source surface to provide power to each component disposed on the power source surface, a ground surface having a reference voltage, a strip line which passes through the power source surface and/or the ground surface so as to transmit signals between components, an antenna installed in proximity to a sectional region of the power source surface and the ground surface, and an electromagnetic wave reduction member which is provided between the power source surface and the ground surface to effectively reduce an electromagnetic wave generated from the strip line.
    Type: Application
    Filed: January 7, 2008
    Publication date: August 21, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hark Byeong PARK, Byong Su Seol, Hyung Geun Kim, Hyun Ho Park, Jong Sung Lee, Hyung Seok Lee, Young Jun Moon
  • Publication number: 20080157326
    Abstract: An IC package including a plurality of BGA IC packages stacked on a printed circuit board and a method of manufacturing the same. The IC package includes a printed circuit board, a first BGA IC package, having a plurality of first solder balls, stacked on the printed circuit board, a second BGA IC package, having a plurality of second solder balls, stacked on the first BGA IC package, and an interposer having a plurality of through-holes, which are filled by the second solder balls in a molten state such that the length of the second solder balls increases while the second solder balls harden, the interposer being joined to the top of the first BGA IC package.
    Type: Application
    Filed: October 16, 2007
    Publication date: July 3, 2008
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Hyun Joo HAN, Tao Sang Park, Se Yeong Jang, Young Jun Moon, Jung Hyeon Kim, Sung Wook Kang
  • Publication number: 20070007322
    Abstract: A board assembly apparatus and a manufacturing method includes applying solder paste onto a first surface of a first board, arranging electronic components on the first surface of the first board on which the solder paste is applied, arranging a second board above the electronic components and the first surface of the first board, and curing the solder paste.
    Type: Application
    Filed: January 5, 2006
    Publication date: January 11, 2007
    Inventors: Jong-sung Lee, Yoon-sung Kim, Young-jun Moon, Se-young Jang
  • Publication number: 20060139044
    Abstract: A test unit usable with a board having, an electronic component includes at least one testing point provided in each electronic component to test electric properties and a connection state of the plurality of electronic components connected to the board. The test unit usable with a PCB having the electronic component includes a testing point formed on the electronic component, thereby an enhancing high integration of the board.
    Type: Application
    Filed: December 27, 2005
    Publication date: June 29, 2006
    Inventors: Tae-sang Park, Jung-soon Kim, Young-jun Moon, Jun-young Lee
  • Publication number: 20060139043
    Abstract: A test unit to test a board having an area array package mounted therein includes the board, the area array package having an electronic component, a plurality of package pins including a plurality of contact pins connected with the electronic component and a plurality of no-contact pins not connected with the electronic component, and a plurality of contact members respectively provided on the plurality of contact pins and the plurality of no-contact pins to connect the plurality of package pins with the board, a plurality of board contact parts provided on the board and connected with the plurality of contact members to be connected with the plurality of package pins, at least one first connection part provided in the area array package to electrically connect the plurality of no-contact pins with each other in pairs, at least one second connection part provided on the board to electrically connect the plurality of board contact parts with each other in pairs to form a circuit line arranged alternately with
    Type: Application
    Filed: December 27, 2005
    Publication date: June 29, 2006
    Inventors: Se-young Jang, Masaharu Tsukue, Young-jun Moon
  • Patent number: 6849477
    Abstract: A method of fabricating and mounting a flip chip includes using an environmentally friendly plasma gas, which minimizes safety hazards during an implementation of the method and does not require an additional heat source during a reflow process thereof. That is, the method includes reflowing a solder bump using an argon-hydrogen plasma process. The argon-hydrogen plasma process used to fabricate the flip chip includes maintaining a pressure in a chamber at 250 to 270 mtorr, feeding a mixed gas of argon with 10 to 20% hydrogen to the chamber to generate a plasma with power of 100 to 200 W, and exposing the flip chip to the plasma for 30 to 120 seconds. Additionally, an argon-hydrogen plasma process used to mount the flip chip includes maintaining pressure in a chamber at 100 to 400 mtorr, feeding a mixed gas of argon with 0 to 20% hydrogen to the chamber to generate a plasma with power of 10 to 50 W, and exposing the flip chip to the plasma for 10 to 120 seconds.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: February 1, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soon-Min Hong, Young-Jun Moon, Min-Young Park, Sea-Gwang Choi
  • Publication number: 20040072387
    Abstract: A method of fabricating and mounting a flip chip includes using an environmentally friendly plasma gas, which minimizes safety hazards during an implementation of the method and does not require an additional heat source during a reflow process thereof. That is, the method includes reflowing a solder bump using an argon-hydrogen plasma process. The argon-hydrogen plasma process used to fabricate the flip chip includes maintaining a pressure in a chamber at 250 to 270 mtorr, feeding a mixed gas of argon with 10 to 20% hydrogen to the chamber to generate a plasma with power of 100 to 200 W, and exposing the flip chip to the plasma for 30 to 120 seconds. Additionally, an argon-hydrogen plasma process used to mount the flip chip includes maintaining pressure in a chamber at 100 to 400 mtorr, feeding a mixed gas of argon with 0 to 20% hydrogen to the chamber to generate a plasma with power of 10 to 50 W, and exposing the flip chip to the plasma for 10 to 120 seconds.
    Type: Application
    Filed: February 25, 2003
    Publication date: April 15, 2004
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soon-Min Hong, Young-Jun Moon, Min-Young Park, Sea-Gwang Choi