Abstract: Disclosed is a method of manufacturing a high voltage transistor in a flash memory device. The method can prohibit a punch leakage current of an isolation film while satisfying active characteristics of the high voltage transistor without the need for a mask process for field stop of the high voltage transistor ion implantation process and a mask removal process.

Abstract: A method of manufacturing a NAND flash device which can improve uniformity of disturb fail characteristics by performing an annealing process after an ion implantation process for forming a P well, reduce a fail bit count by performing an annealing process after an ion implantation process for controlling a threshold voltage and before a process for forming a high voltage gate oxide film, and prevent disturb fail by omitting an STI ion implantation process in a cell region.

Abstract: A method of manufacturing a flash memory cell. The method includes controlling a wall sacrificial oxidization process, a wall oxidization process and a cleaning process of a trench insulating film that are performed before/after a process of forming the trench insulating film for burying a trench to etch the trench insulating film to a desired space. Therefore, it is possible to secure the coupling ratio of a floating gate by maximum and implement a device of a smaller size.

Abstract: Disclosed is a method of manufacturing a high voltage transistor in a flash memory device. The method can prohibit a punch leakage current of an isolation film while satisfying active characteristics of the high voltage transistor without the need for a mask process for field stop of the high voltage transistor ion implantation process and a mask removal process.

Abstract: A method of manufacturing a flash memory cell. The method includes controlling a wall sacrificial oxidization process, a wall oxidization process and a cleaning process of a trench insulating film that are performed before/after a process of forming the trench insulating film for burying a trench to etch the trench insulating film to a desired space. Therefore, it is possible to secure the coupling ratio of a floating gate by maximum and implement a device of a smaller size.

Abstract: There is disclosed a method of manufacturing a flash memory device by which an insulating film spacer is formed on both sidewalls of a gate electrode and a drain region is then formed. Thus, the present invention can improve coverage during a deposition process for forming a select gate and reduce the overlapping area of a floating gate and a drain region. Therefore, as the resistance of the select gate itself is reduced depending on the coverage, the present invention can increase the operating speed of a device and can improve the erase characteristic by F-N tunneling due to reduced overlapping area.