Abstract: High speed multiplexers include a first N-to-1 selection circuit, where N is an integer greater than one, a second N-to-1 selection circuit and an output driver. The first N-to-1 selection circuit is configured to route a true or complementary version of a selected first input signal (from amongst N input signals) to an output thereof in response to a first multi-bit selection signal, where N is an integer greater than one. The second N-to-1 selection circuit is configured to route a true or complementary version of the selected first input signal to an output thereof in response to a second multi-bit selection signal. The output driver includes a pull-up circuit, which is responsive to a signal generated at the output of the first N-to-1 selection circuit, and a pull-down circuit, which is responsive to a signal generated at the output of the second N-to-1 selection circuit.

Abstract: High speed multiplexers include a first N-to-1 selection circuit, where N is an integer greater than one, a second N-to-1 selection circuit and an output driver. The first N-to-1 selection circuit is configured to route a true or complementary version of a selected first input signal (from amongst N input signals) to an output thereof in response to a first multi-bit selection signal, where N is an integer greater than one. The second N-to-1 selection circuit is configured to route a true or complementary version of the selected first input signal to an output thereof in response to a second multi-bit selection signal. The output driver includes a pull-up circuit, which is responsive to a signal generated at the output of the first N-to-1 selection circuit, and a pull-down circuit, which is responsive to a signal generated at the output of the second N-to-1 selection circuit.

Abstract: A mask used for a Lithographie, Galvanofomung, and Abformung (LIGA) process, a method for manufacturing the mask, and a method for manufacturing a microstructure using a LIGA process.

Abstract: A two-dimensional circuit for a traveling-wave tube for millimeter and sub-millimeter electromagnetic waves synchronously interacts with an electron beam in a vacuum electronic microwave amplifier or oscillator. The circuit is a solid body having a length along the tube axis. The solid body has an electrically conductive top section and an electrically conductive bottom section. The top section is configured with a plurality of vertical vanes having a width and height and configured parallel to each other. The bottom section is similarly configured such that when the circuit is viewed in cross section along the length, the vanes on the bottom section are staggered with respect to the vanes on the top section. The top section and the bottom section are separated from each other to define a tunnel through the solid body along the length.

Abstract: Provided are a circuit and a method of detecting clock delay where the circuit to detect clock delay includes a delay detection circuit and a clock forwarding circuit, the delay detection circuit detects a delay between a predetermined output clock signal and an input clock signal, if the detected delays are identical to one another, the circuit generates an initial parameter corresponding to the delay and if the detected delays are not identical to one another, continuously detects the delay until the detected delays are identical to one another, and generates a reset control signal in response to a system reset signal or a predetermined internal reset signal; the clock forwarding circuit loads and unloads the input data in response to the initial parameter, the circuit to detect clock delay can automatically detect the clock delay necessary for setting the initial parameter of the clock forwarding circuit and reset a master circuit and an external circuit that interfaces with the master circuit, thus perfor

Abstract: A mask used for a Lithographie, Galvanofomung, and Abformung (LIGA) process, a method for manufacturing the mask, and a method for manufacturing a microstructure using a LIGA process.

Abstract: For distributing a signal to loads in an area, the area is divided into a plurality of regions. A respective signal point is disposed in each region for providing the signal to a load in the region. A respective diffusion point is disposed between any two neighboring signal points. The signal is initially applied to a center point of the signal and diffusion points. The signal when received at a given signal or diffusion point is transmitted to any of the signal or diffusion points within a maximum distance from the given signal or diffusion point.

Abstract: A semiconductor integrated circuit device has a normal operation mode and a scan test operation mode, and includes a pulse generating circuit and a scan flip-flop circuit. The pulse generating circuit generates pulse signals synchronized with a clock signal in each of the normal and scan test operation modes. The scan flip-flop circuit latches data in response to the pulse signals from the pulse generating circuit signal in each of the normal and scan test operation modes.

Abstract: A level shifter and method thereof. The example level shifter may include a level shifting unit generating a plurality of internal voltages, shifting the voltage levels of a plurality of input signals and outputting an output signal based at least in part on the plurality of internal voltages and a mode control unit controlling the voltage levels of the plurality of internal voltages in response to a mode selection signal. The example method may include generating a plurality of internal voltages based on a plurality of input signals, controlling the voltage levels of the plurality of internal voltages based on a mode selection signal and outputting an output signal based at least in part on the plurality of internal voltages.

Abstract: For distributing a signal to loads in an area, the area is divided into a plurality of regions. A respective signal point is disposed in each region for providing the signal to a load in the region. A respective diffusion point is disposed between any two neighboring signal points. The signal is initially applied to a center point of the signal and diffusion points. The signal when received at a given signal or diffusion point is transmitted to any of the signal or diffusion points within a maximum distance from the given signal or diffusion point.

Abstract: A semiconductor integrated circuit includes a boundary scan register and a plurality of local monitor circuits. The local monitor circuits are arranged individually about peripheral circuit regions of a semiconductor integrated circuit, being spaced from the boundary scan register, in order to measure and predict operation speeds in accordance with local on-chip process variations at a plurality of locations on the peripheral circuit regions. The operational speed of the semiconductor integrated circuit is determined by taking correlations into account between an overall signal delay time measured by the boundary scan register and local signal delay times measured by the respective local monitor circuits.

Abstract: Asemiconductor integrated circuit devices has a normal operation mode and a scan test operation mode, and includes a pulse generating circuit and a scan flip-flop circuit. The pulse generating circuit generates pulse signals synchronized with a clock signal in each of the normal and scan test operation modes. The scan flip-flop circuit latches data in response to the pulse signals from the pulse generating circuit signal in each of the normal and scan test operation modes.

Abstract: Provided are a circuit and a method of detecting clock delay where the circuit to detect clock delay includes a delay detection circuit and a clock forwarding circuit, the delay detection circuit detects a delay between a predetermined output clock signal and an input clock signal, if the detected delays are identical to one another, the circuit generates an initial parameter corresponding to the delay and if the detected delays are not identical to one another, continuously detects the delay until the detected delays are identical to one another, and generates a reset control signal in response to a system reset signal or a predetermined internal reset signal; the clock forwarding circuit loads and unloads the input data in response to the initial parameter, the circuit to detect clock delay can automatically detect the clock delay necessary for setting the initial parameter of the clock forwarding circuit and reset a master circuit and an external circuit that interfaces with the master circuit, thus perfor

Abstract: A clock forwarding circuit automatically detects the delay in transmission of data between a master circuit such as a central processing unit and a slave circuit such as a semiconductor memory and forwards clocks corresponding to the delay. The master circuit includes a clock forwarding circuit which generates a clock signal. The slave circuit is coupled to the master circuit and generates a second clock signal which is synchronized with the first clock signal. The clock forwarding circuit receives the second clock signal, detects delay between the first and second clock signals and sets initial data load/unload parameters of the master circuit based on the detected delay. By forwarding clocks, the data transmission between the clocked circuits can be performed in faultless fashion independently of the delay.

Abstract: A semiconductor integrated circuit includes a boundary scan register and a plurality of local monitor circuits. The local monitor circuits are arranged individually about peripheral circuit regions of a semiconductor integrated circuit, being spaced from the boundary scan register, in order to measure and predict operation speeds in accordance with local on-chip process variations at a plurality of locations on the peripheral circuit regions. The operational speed of the semiconductor integrated circuit is determined by taking correlations into account between an overall signal delay time measured by the boundary scan register and local signal delay times measured by the respective local monitor circuits.

Abstract: A method for controlling display video data on an LCD panel having a display matrix of pixels arranged in rows and columns and having a delta structure, which includes the steps of displaying the video data in its original (unchanged) form during a first field of the video data, and displaying the video data in a modified form during a second field of the video data, with alternate (e.g., odd-numbered) lines of the video data being shifted one pixel towards a first (e.g., right) side of the display matrix. A control circuit for implementing this method generates first and second control signals for controlling the operation of a column driving circuit which drives the columns of pixels of the display matrix in the appropriate manner.