Patents by Inventor Young-Ok Kim
Young-Ok Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080047576Abstract: In a single-substrate type apparatus for processing a substrate, the apparatus includes a chamber, a bottom panel, a solution supplying part and a substrate holder. The chamber has an upper portion and a lower portion. The bottom panel is detachably connected to the lower portion. The solution supplying part is connected to the bottom panel to supply a processing solution to the substrate in the chamber. The substrate holder provides the substrate into the chamber, the substrate holder holding both side portions of the substrate such that the substrate is vertically arranged.Type: ApplicationFiled: August 23, 2007Publication date: February 28, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Ok KIM, Chang-Ki HONG, Kun-Tack LEE, In-Gi KIM, Woo-Gwan SHIM, Jeong-Nam HAN, Kang-Youn LEE
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Patent number: 7074683Abstract: A semiconductor device comprises a device isolation layer disposed in a portion of a substrate of first conductivity type. An outline of the device isolation layer defines an active region of the substrate. An impurity diffused region of second conductivity type may be formed in a portion of the active region; and a silicide layer may be formed to cover the impurity diffused region of second conductivity type. The device isolation layer may include a recess formed therein to expose a portion of the substrate of first conductivity type adjacent to the impurity diffused region of second conductivity type. The silicide layer that is formed to cover the impurity diffused layer of second conductivity type may extend over and against the exposed region of the substrate of first conductivity type that was exposed by the recess of the device isolation layer.Type: GrantFiled: March 8, 2004Date of Patent: July 11, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-Ha Hwang, Young-Ok Kim, Cha-Dong Yeo
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Patent number: 7041594Abstract: A first conduction type well is formed in a substrate, and a second conduction type impurity region is formed in the well. A lower interlayer dielectric is formed on the substrate, including the well and the impurity region. A contact plug, connected to the impurity region through the lower interlayer dielectric, is formed with a void inside it. An upper interlayer dielectric is formed on the lower interlayer dielectric and the contact plug. The upper interlayer dielectric is selectively etched, forming an interconnection groove exposing the contact plug. The contact plug and the exposed void are overetched, extending the void into the first conduction type well. The interconnection groove is filled with a conductive layer, forming an interconnection. A seam extending to the well is formed in the void, connecting the contact plug to the well. Due to the seam, a well bias may be applied to the well.Type: GrantFiled: August 24, 2004Date of Patent: May 9, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Ok Kim, Soon-Byung Park
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Publication number: 20050026329Abstract: A first conduction type well is formed in a substrate, and a second conduction type impurity region is formed in the well. A lower interlayer dielectric is formed on the substrate, including the well and the impurity region. A contact plug, connected to the impurity region through the lower interlayer dielectric, is formed with a void inside it. An upper interlayer dielectric is formed on the lower interlayer dielectric and the contact plug. The upper interlayer dielectric is selectively etched, forming an interconnection groove exposing the contact plug. The contact plug and the exposed void are overetched, extending the void into the first conduction type well. The interconnection groove is filled with a conductive layer, forming an interconnection. A seam extending to the well is formed in the void, connecting the contact plug to the well. Due to the seam, a well bias may be applied to the well.Type: ApplicationFiled: August 24, 2004Publication date: February 3, 2005Applicant: Samsung Electronics Co., Ltd.Inventors: Young-Ok Kim, Soon-Byung Park
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Patent number: 6838737Abstract: A first conduction type well is formed in a substrate, and a second conduction type impurity region is formed in the well. A lower interlayer dielectric is formed on the substrate, including the well and the purity region. A contact plug, connected to the impurity region through the lower interlayer dielectric, is formed with a void inside it. An upper interlayer dielectric is formed on the lower interlayer dielectric and the contact plug. The upper interlayer dielectric is selectively etched, forming an interconnection groove exposing the contact plug. The contact plug and the exposed void are overetched, extending the void into the first conduction type well. The interconnection groove is filled with a conductive layer, forming an interconnection. A seam extending to the well is formed in the void, connecting the contact plug to the well. Due to the seam, a well bias may be applied to the well.Type: GrantFiled: July 29, 2003Date of Patent: January 4, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Ok Kim, Soon-Byung Park
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Publication number: 20040180502Abstract: A semiconductor device comprises a device isolation layer disposed in a portion of a substrate of first conductivity type. An outline of the device isolation layer defines an active region of the substrate. An impurity diffused region of second conductivity type may be formed in a portion of the active region; and a silicide layer may be formed to cover the impurity diffused region of second conductivity type. The device isolation layer may include a recess formed therein to expose a portion of the substrate of first conductivity type adjacent to the impurity diffused region of second conductivity type. The silicide layer that is formed to cover the impurity diffused layer of second conductivity type may extend over and against the exposed region of the substrate of first conductivity type that was exposed by the recess of the device isolation layer.Type: ApplicationFiled: March 8, 2004Publication date: September 16, 2004Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-Ha Hwang, Young-Ok Kim, Cha-Dong Yeo
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Patent number: 6730971Abstract: A semiconductor device comprises a device isolation layer disposed in a portion of a substrate of first conductivity type. An outline of the device isolation layer defines an active region of the substrate. An impurity diffused region of second conductivity type may be formed in a portion of the active region; and a silicide layer may be formed to cover the impurity diffused region of second conductivity type. The device isolation layer may include a recess formed therein to expose a portion of the substrate of first conductivity type adjacent to the impurity diffused region of second conductivity type. The silicide layer that is formed to cover the impurity diffused layer of second conductivity type may extend over and against the exposed region of the substrate of first conductivity type that was exposed by the recess of the device isolation layer.Type: GrantFiled: November 6, 2002Date of Patent: May 4, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-Ha Hwang, Young-Ok Kim, Cha-Dong Yeo
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Publication number: 20040036177Abstract: A first conduction type well is formed in a substrate, and a second conduction type impurity region is formed in the well. A lower interlayer dielectric is formed on the substrate, including the well and the impurity region. A contact plug, connected to the impurity region through the lower interlayer dielectric, is formed with a void inside it. An upper interlayer dielectric is formed on the lower interlayer dielectric and the contact plug. The upper interlayer dielectric is selectively etched, forming an interconnection groove exposing the contact plug. The contact plug and the exposed void are overetched, extending the void into the first conduction type well. The interconnection groove is filled with a conductive layer, forming an interconnection. A seam extending to the well is formed in the void, connecting the contact plug to the well. Due to the seam, a well bias may be applied to the well.Type: ApplicationFiled: July 29, 2003Publication date: February 26, 2004Inventors: Young-Ok Kim, Soon-Byung Park
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Publication number: 20030111708Abstract: A semiconductor device comprises a device isolation layer disposed in a portion of a substrate of first conductivity type. An outline of the device isolation layer defines an active region of the substrate. An impurity diffused region of second conductivity type may be formed in a portion of the active region; and a silicide layer may be formed to cover the impurity diffused region of second conductivity type. The device isolation layer may include a recess formed therein to expose a portion of the substrate of first conductivity type adjacent to the impurity diffused region of second conductivity type. The silicide layer that is formed to cover the impurity diffused layer of second conductivity type may extend over and against the exposed region of the substrate of first conductivity type that was exposed by the recess of the device isolation layer.Type: ApplicationFiled: November 6, 2002Publication date: June 19, 2003Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-Ha Hwang, Young-Ok Kim, Cha-Dong Yeo
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Publication number: 20010026813Abstract: Disclosed are a Scutellariae Radix extract and a pharmaceutical preparation comprising the extract as a pharmaceutically effective ingredient. With significant neuroprotective activity, but no toxicity, the Scutellariae Radix extract is suitable for use in the prophylaxis and treatment of brain diseases, such as apoplexy, Parkinson's disease and senile dementia.Type: ApplicationFiled: February 6, 2001Publication date: October 4, 2001Inventors: Ho-Cheol Kim, Duk-Kyun Ahn, Sun-Yeou Kim, Kyungho Suk, Young-Ok Kim, Kang-Hyun Leem
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Patent number: 6277623Abstract: This invention relates to a strain of E.coli JM83/pKP2 transformed by a plasmid and phytase produced therefrom, and more particularly, to the strain E.coli JM83/pKP2 transformed with a recombinant vector pKP1 or pKP2, so prepared by gene manipulation.Type: GrantFiled: April 27, 2000Date of Patent: August 21, 2001Assignees: Daesung Microbiological Labs. Co., Ltd., Korea Institute of Science and TechnologyInventors: Tae Kwang Oh, Young Ok Kim, Hyung Kwoun Kim, Seung Chun Park, Dong Kyoo Lee, Jung Kee Lee
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Patent number: 6255098Abstract: The strain Bacillus sp. DS11 (KCTC 0231BP) is disclosed and a phytase produced by DS11 having the following characteristics: optimum temperature: 65° C.; optimum pH: 7.0; molecular weight: 43,000 dalton; isoelectric point: 5.6; and a specified N-terminal amino acid sequence. The bacterial strain DS11 or the phytase it produces can be used as an animal feed additive.Type: GrantFiled: December 16, 1998Date of Patent: July 3, 2001Assignee: Korea Institute of Science and TechnologyInventors: Tae Kwang Oh, Hyung Kwon Kim, Kyung Suk Bae, Young Seo Park, Young Ok Kim, Yang Woong Choi, Dong Kyu Lee, Jung Kee Lee
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Patent number: 5989968Abstract: In a bipolar transistor and the manufacturing method thereof, the bipolar transistor includes a first conductive well, an emitter impurity layer formed in the center of the well, a base impurity layer formed in the form of completely surrounding the emitter impurity layer, and a first conductive high-concentration collector impurity layer having an annular shape along the edge of the well, and maintaining a constant interval from the base impurity layer. The first conductive layer formed to be parallel with the high-concentration collector impurity layer is connected therewith through a contact hole, and is connected with the collector electrode through another contact hole. Owing to a simple manufacturing process, the processing time and cost can be reduced. Also, parasitic bipolar transistors are not generated nor is increased collector resistance produced, thereby increasing reliability.Type: GrantFiled: September 17, 1997Date of Patent: November 23, 1999Assignee: Samsung Electronics Co., Ltd.Inventors: Young-ok Kim, Soo-cheol Lee
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Patent number: 5814538Abstract: A method for forming a bipolar transistor comprises the following steps. A collector region of a first conductivity type is formed in a substrate adjacent a surface thereof. A base region of a second conductivity type is then formed in the collector region adjacent the surface of the substrate. A base electrode is formed on a first portion of the substrate adjacent the base region wherein the base electrode comprises a dopant of the second conductivity type. Next, an emitter electrode is formed on a second portion of the substrate adjacent the base region wherein the emitter electrode comprises a dopant of the first conductivity type. The dopant of the second conductivity type from the base electrode is diffused into the first portion of the base region to increase a dopant concentration of the first portion of the base region adjacent the base electrode.Type: GrantFiled: March 19, 1997Date of Patent: September 29, 1998Assignee: Samsung Electronics Co., Ltd.Inventors: Young-ok Kim, Jong-mil Youn